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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16306-1E
32-bit Proprietary Microcontrollers
CMOS
FR30 Family
MB91150 Series
MB91F155/MB91154
s DESCRIPTION
The MB91150 is a single-chip microcontroller using a RISC-CPU (FR 30 series) as its core. It contains peripheral I/O resources suitable for audio, MD and so on which are required to operate at low power consumption.
s FEATURES
1. CPU
* * * * * * * * 32-bit RISC (FR30) , load/store architecture, 5-stage pipeline General-purpose registers: 32 bits x16 16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle Memory-to-memory transfer, bit processing, barrel shift processing : Optimized for embedded applications Function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems supporting high level languages Register interlock functions, efficient assembly language description Branch instructions with delay slots : Reduced overhead time in branching executions Internal multiplier/supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles Interrupt (PC and PS saving) : 6 cycles, 16 priority levels (Continued)
*
s PACKAGE
144-pin plastic LQFP
(FPT-144P-M08)
MB91F155/MB91154
2. Bus Interface
* * * * * 16-bit address output, 8/16-bit data input and output Basic bus cycle : 2-clock cycle Support for interface for various types of memory Unused data/address pins can be configured us input/output ports Support for little endian mode
3. Internal ROM
MB91F155 FLASH products : 510 Kbytes MB91154 Mask product : 384 Kbytes
4. Internal RAM
Mask, FLASH products : 2 Kbytes
5. Internal Backup RAM
MB91F155 FLASH products : 32 Kbytes MB91154 Mask product : 20 Kbytes More power can be saved by entering backup mode and then applying power supply current only to the backup RAM.
6. DMAC
DMAC in descriptor format for placing transfer parameters on to the main memory. Capable of transferring a maximum of eight internal and external factors combined. Three channels for external factors
7. Bit Search Module
Searches in one cycle for the position of the bit that changes from the MSB in one word to the initial I/O.
8. Timers
* 16-bit OCU x 8 channels, ICU x 4 channels, Free-run timer x 1 channel * 8/16-bit up/down timer/counter (8-bit x 2 channels or 16-bit x 1 channel) AIN and BIN share pins with internal interrupts. * 16-bit PPG timer x 6 channels. The output pulse cycle and duty can be varied as desired * 16-bit reload timer x 4 channels * 8-bit x 3 channels * 10-bit x 8 channels * Sequential conversion method (conversion time : 5.0 s@33 MHz) * Single conversion or scan conversion can be selected, and one-shot or continuous or stop conversion mode can be set respectively. * Conversion starting function by hardware/software. (Continued)
9. D/A Converter
10. A/D Converter (Sequential Comparison Type)
2
MB91F155/MB91154
(Continued)
11. Serial I/O
* UART x 4 channels. Any of them is capable of serial transfer in sync with clock attached with the LSB/MSB switching function. * Serial data output and serial clock output are selectable by push-pull/open drain software. * A 16-bit timer (U-timer) is contained as a dedicated baud rate generator allowing any baud rate to be generated. * One channel master/slave send and receive * Arbitration and clock synchronization functions (The product is licensed with the Philips I2C patent to support those customers who intend to use this product in an I2C system in compliance with the standard I2C specification stipulated by Philips.)
12. I2C Bus Interface
13. Clock Switching Function
* Gear function : Operating clock ratios to the basic clock can be set independently for the CPU and peripherals from four types, 1 : 1, 1 : 2, 1 : 4 or 1 : 8.
14. Clock Function (Calendar Macro)
* Internal 32 kHz clock function * Capable of operating in clock mode to run only the clock function while the CPU and peripheral macros are stopped.
15. Interrupt Controller
External interrupt input (16 channels in total) : * Allows the rising edge/falling edge/H level/L level to be set. Internal interrupt factors : * Interrupt by resources and delay interrupt
16. Others
* * * * * Reset cause : Power on reset/watchdog timer/software reset/external reset Low power consumption mode : Sleep/stop/clock mode Package : LQFP 144-pin CMOS technology (0.35 m) Power supply voltage : 3.15 V to 3.6 V
3
MB91F155/MB91154
s PIN ASSIGNMENT
(TOP VIEW)
VSS X1A X0A BACKUP VCC2 PK7/AN7 PK6/AN6 PK5/AN5 PK4/AN4 PK3/AN3 PK2/AN2 PK1/AN1 PK0/AN0 AVSS AVRL AVRH AVCC DAVC DAVS DA0 DA1 DA2 VCC PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0 PL1/DACK0 PL0/DREQ0 PH0/SIN0 PH1/SOT0 PH2/SCK0/TO0 PH3/SIN1 PH4/SOT1 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 VSS P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 VSS VCC P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 P60/A16 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
PH5/SCK1/TO1 PI0/SIN2 PI1/SOT2 PI2/SCK2/TO2 PI3/SIN3 PI4/SOT3 PI5/SCK3/TO3 VSS PJ0/SCL PJ1/SDA VSS VCC PG5/PPG5 PG4/PPG4 PG3/PPG3 PG2/PPG2 PG1/PPG1 PG0/PPG0 PF4/FRCK PF3/IN3 PF2/IN2 PF1/IN1 PF0/IN0 PE7/OC7 PE6/OC6 PE5/OC5 PE4/OC4 PE3/OC3 PE2/OC2 PE1/OC1 PE0/OC0 VCC PD7/ATG/INT15 PD6/DEOP2/INT14 PD5/ZIN1/INT13/TRG5 PD4/ZIN0/INT12/TRG4
4
P61/A17 P62/A18 P63/A19 P64/A20 P65/A21 P66/A22 P67/A23 VSS P80/RDY P81/BGRNT P82/BRQ P83/RD P84/WR0 P85/WR1 P86/CLK MD2 MD1 MD0 RST VCC X1 X0 VSS PC0/INT0 PC1/INT1 PC2/INT2 PC3/INT3 PC4/INT4/CS0 PC5/INT5/CS1 PC6/INT6/CS2 PC7/INT7/CS3 VCC PD0/AIN0/INT8/TRG0 PD1/BIN0/INT9/TRG1 PD2/AIN1/INT10/TRG2 PD3/BIN1/INT11/TRG3
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
(FPT-144P-M08)
MB91F155/MB91154
s PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin name D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28P34 D29/P35 D30/P36 D31/P37 A00/P40 A01/P41 A02/P42 A03/P43 A04/P44 A05/P45 A06/P46 A07/P47 A08/P50 A09/P51 A10/P52 A11/P53 A12/P54 A13/P55 A14/P56 A15/P57 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 Circuit type Function
C
Bit 16 to bit 23 of external data bus These pins are enabled only in 16-bit external bus mode. These pins are available as ports in single-chip and 8-bit external bus modes.
C
Bit 24 to bit 31 of external data bus These pins are available as ports in single-chip mode.
F
Bit 0 to bit 15 of external address bus These pins are enabled in external bus mode. These pins are available as ports in single-chip mode.
O
Bit 16 to bit 23 of external address bus These pins are available as ports when the address bus is not in use.
45
RDY/P80
C
External RDY input This function is enabled when external RDY input is allowed. Input "0" when the bus cycle being executed does not end. This pin is available as a port when external RDY input is not in use.
(Continued)
5
MB91F155/MB91154
Pin No.
Pin name
Circuit type
Function External bus release acceptance output This function is enabled when external bus release acceptance output is allowed. Output "L" upon releasing of the external bus. This pin is available as a port when external bus release acceptance output is not allowed. External bus release request input This function is enabled when external bus release request input is allowed. Input "1" when the release of the external bus is desired. This pin is available as a port when external bus release request input is not in use. External bus read strobe output This function is enabled when external bus read strobe output is allowed. This pin is available as a port when external bus read strobe output is not allowed. External bus write strobe output This function is enabled in external bus mode. This pin is available as a port in single chip mode. External bus write strobe output This function is enabled in external bus mode when the bus width is 16 bits. This pin is available as a port in single chip mode or when the external bus width is 8 bits. System clock output The pin outputs the same clock as the external bus operating frequency. The pin is available as a port when it is not used to output the clock. Mode pins To use these pins, connect them directly to either Vcc or Vss. Use these pins to set the basic MCU operating mode. External reset input High-speed clock oscillation pins (16.5 MHz) External interrupt request input 0-3 Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. Since this port is allowed to input also in standby mode, it can be used to reset the standby state. These pins are available as ports when external interrupt request input is not in use.
46
BGRNT/P81
F
47
BRQ/P82
C
48
RD/P83
F
49
WR0/P84
F
50
WR1/P85
F
51 52 53 54 55 57 58
CLK/P86 MD2 MD1 MD0 RST X1 X0
F
G B A
60 61 62 63
INT0/PC0 INT1/PC1 INT2/PC2 INT3/PC3
H
(Continued)
6
MB91F155/MB91154
Pin No.
Pin name
Circuit type
Function These pins also serve as the chip select output and external interrupt request input 4-7. When the chip select output is not allowed, these pins are available as external interrupt requests or ports. Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. Since this port is also allowed to input in standby mode, the port can be used to reset the standby state. These pins are available as ports when external interrupt request input and chip select output are not in use. External interrupt request input 8-13 Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. [AIN, BIN] Up/down timer input. [TRG] PPG external trigger input. Since this input is used more or less continuously while input is allowed, output by the port needs to be stopped except when it is performed deliberately. These pins are available as ports when the external interrupt request input, up timer counter input, and PPG external trigger input are not in use. External interrupt request input 14 Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. [DEOP2] DMA external transfer end output. This function is enabled when DMAC external transfer end output is allowed. This pin is available as a port when it is not in use as the external interrupt request input or DMA external transfer end output. External interrupt request input 15 Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. [ATG] A/D converter external trigger input. Since this input is used more or less continuously when selected as an A/D activation factor, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when it is not in use as the external interrupt request input or A/D converter external trigger input.
64 65 66 67
INT4/PC4/CS0 INT5/PC5/CS1 INT6/PC6/CS2 INT7/PC7/CS3
H
69 70 71 72 73 74
PD0/AIN0/INT8/TRG0 PD1/BIN0/INT9/TRG1 PD2/AIN1/INT10/TRG2 PD3/BIN1/INT11/TRG3 PD4/ZIN0/INT12/TRG4 PD5/ZIN1/INT13/TRG5
H
75
PD6/DEOP2/INT14
H
76
PD7/ATG/INT15
H
(Continued)
7
MB91F155/MB91154
Pin No. 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
Pin name PE0/OC0 PE1/OC1 PE2/OC2 PE3/OC3 PE4/OC4 PE5/OC5 PE6/OC6 PE7/OC7 PF0/IN0 PF1/IN1 PF2/IN2 PF3/IN3 PF4/FRCK PG0/PPG0 PG1/PPG1 PG2/PPG2 PG3/PPG3 PG4/PPG4 PG5/PPG5
Circuit type
Function
F
Output compare output These pins are available as ports when output compare output is not allowed.
F
Input capture input This function is enabled when the input capture operation is input. These pins are available as ports when input capture input is not in use. Free-run timer external clock input pin This pin is available as a port when free-run timer external clock input is not in use.
F
F
PPG timer output This function is enabled when PPG timer output is allowed. These pins are available as ports when PPG timer output is not allowed.
99
PJ1/SDA
Q
I2C interface I/O pin This function is enabled when the I2C interface is allowed to operate. While the I2C interface is in operation, keep the port output set to Hi-Z. This pin is available as a port when the I2C interface is not in use. I2C interface I/O pin This function is enabled when the I2C interface is allowed to operate. While the I2C interface is in operation, keep the port output set to Hi-Z. This pin is available as a port when the I2C interface is not in use. UART3 clock I/O, Reload timer 3 output When UART3 clock output is not allowed, reload timer 3 can be output by allowing it. This pin is available as a port when neither UART3 clock output nor reload timer output is allowed. UART3 data output This function is enabled when UART3 data output is allowed. This pin is available as a port when UART3 clock output is not allowed. UART3 data input Since this input is used more or less continuously while UART3 is engaged in input operations, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when UART3 output data input is not in use.
100
PJ0/SCL
Q
102
PI5/SCK3/TO3
P
103
PI4/SOT3
P
104
PI3/SIN3
P
(Continued)
8
MB91F155/MB91154
Pin No.
Pin name
Circuit type
Function UART2 clock I/O, Reload timer 2 output When UART2 clock output is not allowed, reload timer 2 can be output by allowing it. This pin is available as a port when neither UART2 clock output nor reload timer output is allowed. UART2 data output This function is enabled when UART2 data output is allowed. This pin is available as a port when UART2 clock output is not allowed. UART2 data input Since this input is used more or less continuously while UART2 is engaged in input operations, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when UART2 data input is not in use. UART1 clock I/O, Reload timer 1 output When UART1 clock output is not allowed, reload timer 1 can be output by allowing it. This pin is available as a port when neither UART1 clock output nor reload timer output is allowed. UART1 data output This function is enabled when UART1 data output is allowed. This pin is available as a port when UART1 clock output is not allowed. UART1 data input Since this input is used more or less continuously while UART1 is engaged in input operations, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when UART1 data input is not in use. UART0 clock I/O, Reload timer 0 output When UART0 clock output is not allowed, reload timer 0 can be output by allowing it. This pin is available as a port when neither UART0 clock output nor reload timer output is allowed. UART0 data output This function is enabled when UART0 data output is allowed. This pin is available as a port when UART0 clock output is not allowed. UART0 data input Since this input is used more or less continuously while UART0 is engaged in input operations, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when UART0 data input is not in use. DMA external transfer request input Since this input is used more or less continuously when selected as a DMAC transfer factor, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when DMA external transfer request input is not in use.
105
PI2/SCK2/TO2
P
106
PI1/SOT2
P
107
PI0/SIN2
P
108
PH5/SCK1/TO1
P
109
PH4/SOT1
P
110
PH3/SIN1
P
111
PH2/SCK0/TO0
P
112
PH1/SOT0
P
113
PH0/SIN0
P
114
DREQ0/PL0
F
(Continued)
9
MB91F155/MB91154
Pin No.
Pin name
Circuit type
Function DMA external transfer request acceptance output This function is enabled when the DMAC external transfer request acceptance is allowed to be output. This pin is available as a port when the DMAC transfer request acceptance is not allowed to be output. DMA external transfer end output This function is enabled when the end of DMAC external transfer is allowed to be output. DMA external transfer request input Since this input is used more or less continuously when selected as a DMAC transfer factor, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when DMA external transfer request input is not in use. DMA external transfer request acceptance output This function is enabled when the DMAC external transfer request acceptance is allowed to be output. This pin is available as a port when DMAC transfer request acceptance output is not allowed. DMA external transfer end output This function is enabled when the end of DMAC external transfer is allowed to be output. DMA external transfer request input Since this input is used more or less continuously when selected as a DMAC transfer factor, output by the port needs to be stopped except when it is performed deliberately. This pin is available as a port when DMA external transfer request input is not in use. DMA external transfer request acceptance output This function is enabled when the DMAC external transfer request acceptance is allowed to be output. This pin is available as a port when DMAC transfer request acceptance output is not allowed. D/A converter output This function is enabled when D/A converter output is allowed. Power supply pin for the D/A converter Power supply pin for the D/A converter Vcc power supply for the A/D converter A/D converter reference voltage (high potential side) Be sure to turn on/off this pin with potential higher than AVRH applied to Vcc. A/D converter reference voltage (low potential side) Vss power supply for the A/D converter
115
DACK0/PL1
F
116
DEOP0/PL2
F
117
DREQ1/PL3
F
118
DACK1/PL4
F
119
DEOP1/PL5
F
120
DREQ2/PL6
F
121
DACK2/PL7
F
123 124 125 126 127 128 129 130 131 10
DA2 DA1 DA0 DAVS DAVC AVCC AVRH AVRL AVSS

(Continued)
MB91F155/MB91154
(Continued)
Pin No. 132 133 134 135 136 137 138 139 140 141 142 143 27, 56, 68, 77, 97, 122 9, 26, 44, 59, 98, 101, 144 Pin name AN0/PK0 AN1/PK1 AN2/PK2 AN3/PK3 AN4/PK4 AN5/PK5 AN6/PK6 AN7/PK7 VCC2 BACKUP X0A X1A VCC Circuit type Function
N
A/D converter analog input These pins are enabled when the AIC register is designated for analog input. These pins are available as ports when A/D converter analog input is not in use.
G K
Backup power supply pin Backup circuit protection signal input Low-speed clock (32 kHz) oscillation pin Power supply pin (VCC) for digital circuit Always power supply pin (VCC) must be connected to the power supply Earth level (VSS) for digital circuit Always power supply pin (VSS) must be connected to the power supply
VSS
Note : On the majority of pins listed above, the I/O port and the resource I/O are multiplexed, such as XXXX/Pxx. When the port and the resource output compete against each other on these pins, priority is given to the resource.
11
MB91F155/MB91154
s I/O CIRCUIT TYPE
Type
X1 Xout
Circuit
Remarks * High-speed oscillation circuit (16.5 MHz) Oscillation feedback resistor = approx. 1 M
A
X0
* CMOS hysteresis input pin CMOS hysteresis input (standby control not attached) Pullup resistor B
Digital input
Pout
* CMOS level I/O pin CMOS level output CMOS level input (attached with standby control) IOL = 4 mA
C
R
Nout
CMOS input Standby control
Pout
* CMOS hysteresis I/O pin CMOS level output CMOS hysteresis input (attached with standby control) IOL = 4 mA
F
R
Nout
Hysteresis input Standby control
(Continued)
12
MB91F155/MB91154
Type
Circuit
Remarks * CMOS level input pin CMOS level input (standby control not attached)
G
R Digital input
Pullup control R Pout
H
Nout R Hysteresis input
* CMOS hysteresis I/O pin with pullup control CMOS level output CMOS level input (standby control not attached) Pullup resistance = approx. 50 k (Typ.) IOL = 4 mA * Clock oscillation circuit (32 kHz)
X1A Xout
K
X0A
Pout
Nout
N
R CMOS input Standby control Analog input
* Analog/CMOS level I/O pin. CMOS level output CMOS level input (attached with standby control) Analog input (Analog input is enabled when AIC's corresponding bit is set to "1.") IOL = 4 mA
(Continued)
13
MB91F155/MB91154
(Continued) Type
Circuit
Pullup control Pout
Remarks * CMOS hysteresis I/O pin with pullup control CMOS level output CMOS hysteresis input (attached with standby control) Pullup resistance = approx. 50 k (Typ.) IOL = 4 mA
R
O
R
Nout
Hysteresis input Standby control
Pullup control
R
Open drain control
P
R
Nout
* CMOS hysteresis I/O pin with pullup control. CMOS level output (attached with open drain control) CMOS hysteresis input (attached with standby control) Pullup resistance = approx. 50 k (Typ.) IOL = 4 mA
Hysteresis input Standby control
Nout
* Open drain I/O pin * 5 V tolerance of voltage * CMOS hysteresis input (attached with standby control) IOL = 15 mA
Q
R Hysteresis input Standby control
14
MB91F155/MB91154
s HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating.
2. Treatment of Pins
* Treatment of unused pins Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors. * Treatment of open pins Be sure to use open pins in open state. * Treatment of output pins Shortcircuiting an output pin with the power supply or with another output pin or connecting a large-capacity load may causes a flow of large current. If this conditions continues for a lengthy period of time, the device deteriorates. Take great care not to exceed the absolute maximum ratings. * Mode pins (MD0-MD2) These pins should be used directly connected to either VCC or VSS. In order to prevent noise from causing accidental entry into test mode, keep the pattern length as short as possible between each mode pin and VCC or VSS on the board and connect them with low impedance. * Power supply pins When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND. It is preferred to connect VCC and VSS of MB91F15/MB9115 to power supply with minimal impedance possible. It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 F between VCC and VSS at a position as close as possible to MB91F155/MB91154. * Crystal oscillator circuit Noises around X0, X1, X0A, and X1A pins may cause malfunctions of MB91F155/MB91154. In designing the PC board, layout X0, X1 (X0A, X1A) and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. It is strongly recommended to design PC board so that X0, X1, X0A, and X1A pins are surrounded by grounding area for stable operation. The MB91F155 and MB91154 devices do not contain a feedback resistor. To use the clock function, you need to connect an external resistor.
X0A
X1A MB91F155/MB91154
3. Precautions
* External Reset Input It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly. * External Clocks When using an external clock, normally, a clock of which the phase is opposite to that of X0 must be supplied 15
MB91F155/MB91154
to the X0 and X1 pins simultaneously. However, when using the clock along with STOP (oscillation stopped) mode, the X1 pin stops when "H" is input in STOP mode. To prevent one output from competing against another, an external resistor of about 1 k should be provided. The following figure shows an example usage of an external clock. Figure 2.1 An example usage of an external clock
X0
X1 MB91F155/MB91154
4. Care During Powering Up
* When powering up When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to "H" level. * Source oscillation input At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. * Power on resetting When powering up or when turning the power back on after the supply voltage drops below the operation assurance range, be sure to reset the power. * Power on sequence (When Vcc2 is connected to Vcc) Turn on the power in the order of Vcc, AVcc and AVRH. The power should be disconnected in inverse order. * Even when an AD converter is not in use, connect AVcc to the Vcc level and AVss to the Vss level. * Even when a DA converter is not in use, connect DAVC to the Vcc level and DAVS to the Vss level.
5. Powering Up and Backup Mode
This product type has a backup RAM and a Vcc2 power supply dedicated to the calendar macro. With respect to the Vcc2 and backup pin, adhere to the following : * When turning on only Vcc2 with Vcc turned off, be sure that the BACK UP pin is on the "L" level. * Be sure that the BACK UP pin reaches the "H" level after Vcc is turned on. When Vcc is off, the BACK UP pin must be on the "L" level. * When setting the BACK UP pin from the "H" to "L" level, be sure that the CPU is in stop mode.
VCC2 ON VCC ON CPU operation STOP mode VCC OFF Backing up in progress VCC ON
VCC VCC2 BACK UP
Note : Do not turn on Vcc from Vcc2 off state.
16
MB91F155/MB91154
6. When the Clock Function (Calendar Macro) Is Not in Use
When using only the internal backup RAM (the clock function not in use) , the clock oscillation pin must be configured as shown next.
X0A
OPEN
X1A MB91F155/MB91154
This product type does not allow the clock crystal oscillator to be stopped with software.
17
MB91F155/MB91154
s BLOCK DIAGRAM
(MB91F155) MD0 MD1 MD2 RST M O D E () 4 FR30 CPU Core I - Bus D - Bus OSC (2) X0A X1A PE7/OC7 PE6/OC6 PE5/OC5 PE4/OC4 PE3/OC3 PE2/OC2 PE1/OC1 PE0/OC0 PG5/PPG5 PG4/PPG4 PG3/PPG3 PG2/PPG2 PG1/PPG1 PG0/PPG0 Clock BACKUP VCC2
Calendar P37/D31 (IO) P30/D24 P27/D23 P O R T 3 / 2 () 16 P O R T 6 / 5 / 4 24 P O R T 8 () 7 () I - Bus D - Bus
Backup RAM 32 KB
DATA
P O R T E
Output Compare
P20/D16 P67/A23 (O) P60/A16 P57/A15 Address P50/A8 P47/A7 P40/A0 P86/CLK (O) P85/WR1 (O) P84/WR0 P83/RD (O) P82/BRQ (I) P81/BGRNT (O) P80/RDY (I) PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0 (O) PL1/DACK0 (O) PL0/DREQ0 (I) X0 (I) X1 (I) PD7/INT15/ATG (I) PD6/INT14/DEOP2 PD5/INT13/ZIN1 PD4/INT12/ZIN0 PD3/INT11/BIN1 PD2/INT10/AIN1 PD1/INT9/BIN0 (I) PD0/INT8/AIN0 (I) PC7/INT7/CS3 PC6/INT6/CS2 PC5/INT5/CS1 PC4/INT4/CS0 PC3/INT3 PC2/INT2 PC1/INT1 PC0/INT0 (I)
DMAC 8 ch Bit Search D - Bus R - Bus
() 8 P O R T G () 6
PPG
P O R T UART 4 ch UTIMER 4 ch H () 6
C - Bus External Bus CTL
Bus Control
16 bit Reload Timer 4 ch 16 bit Free RUN Timer 1 ch 16 bit PPG 6 ch
P O R T I () 6
RAM 2 KB P O R T L () 8
PH0/SIN0 PH1/SOT0 PH2/SCK0/TO0 PH3/SIN1 PH4/SOT1 UART PH5/SCK1/TO1 TOX: Reload PI0/SIN2 Timer PI1/SOT2 PI2/SCK2/TO2 PI3/SIN3 PI4/SOT3 PI5/SCK3/TO3
DMAC
ROM 510 KB
()
P O R T J 2
PJ0/SCL PJ1/SDA
I2C
Clock
OSC (2) P O R T D ) ( 8
Clock Control
16 bit Input Capture 4 ch 16 bit Output Compare 8 ch 10 bit 8 input A/D converter
P O R T K () 8
A/D DMAC
Interrupt Controller
PK0/AN0 PK1/AN1 PK2/AN2 PK3/AN3 PK4/AN4 PK5/AN5 PK6/AN6 PK7/AN7 PF4/FRCK PF3/IN3 PF2/IN2 PF1/IN1 PF0/IN0
A/D
Up/Down Counter External Interrupt
P O R T C ( ) 8
External Interrupt 16 ch
8 bit 3 output D/A converter I2C Interface 1 ch
()
8 bit Up/Down Counter 2 ch
P O R T F 5
Free Run Timer Input Capture
D A () 3
DA2 DA1 DA0
18
MB91F155/MB91154
(MB91154) MD0 MD1 MD2 RST M O D E ) ( 4 FR30 CPU Core I - Bus D - Bus
BACKUP
VCC2
Calendar P37/D31 (IO) P30/D24 P27/D23 P O R T 3 / 2 ) ( 16 P O R T 6 / 5 / 4 ( 24 P O R T 8 ( ) 7 I - Bus D - Bus )
OSC (2)
X0A X1A PE7/OC7 PE6/OC6 PE5/OC5 PE4/OC4 PE3/OC3 PE2/OC2 PE1/OC1 PE0/OC0 PG5/PPG5 PG4/PPG4 PG3/PPG3 PG2/PPG2 PG1/PPG1 PG0/PPG0
Clock
Backup RAM 20 KB
DATA
P O R T E
Output Compare
P20/D16 P67/A23 (O) P60/A16 P57/A15 Address P50/A8 P47/A7 P40/A0 P86/CLK (O) P85/WR1 (O) P84/WR0 P83/RD (O) P82/BRQ (I) P81/BGRNT (O) P80/RDY (I) PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0 (O) PL1/DACK0 (O) PL0/DREQ0 (I) X0 (I) X1 (I) PD7/INT15/ATG (I) PD6/INT14/DEOP2 PD5/INT13/ZIN1 PD4/INT12/ZIN0 PD3/INT11/BIN1 PD2/INT10/AIN1 PD1/INT9/BIN0 (I) PD0/INT8/AIN0 (I) PC7/INT7/CS3 PC6/INT6/CS2 PC5/INT5/CS1 PC4/INT4/CS0 PC3/INT3 PC2/INT2 PC1/INT1 PC0/INT0 (I)
DMAC 8 ch Bit Search D - Bus R - Bus
( P O R T G ( ) 6
) 8
PPG
P O R T H ( ) 6
C - Bus UART 4 ch UTIMER 4 ch External Bus CTL
Bus Control
16 bit Reload Timer 4 ch 16 bit Free RUN Timer 1 ch 16 bit PPG 6 ch 16 bit Input Capture 4 ch 16 bit Output Compare 8 ch 10 bit 8 input A/D converter
P O R T I ( ) 6
RAM 2 KB P O R T L ( ) 8
PH0/SIN0 PH1/SOT0 PH2/SCK0/TO0 PH3/SIN1 PH4/SOT1 UART PH5/SCK1/TO1 TOX: Reload PI0/SIN2 Timer PI1/SOT2 PI2/SCK2/TO2 PI3/SIN3 PI4/SOT3 PI5/SCK3/TO3
DMAC
ROM 384 KB
()
P O R T J 2 P O R T K
PJ0/SCL PJ1/SDA
I2C
Clock
OSC (2) P O R T D ) ( 8
Clock Control
Interrupt Controller
Up/Down Counter External Interrupt
(
)
A/D DMAC
8
PK0/AN0 PK1/AN1 PK2/AN2 PK3/AN3 PK4/AN4 PK5/AN5 PK6/AN6 PK7/AN7 PF4/FRCK PF3/IN3 PF2/IN2 PF1/IN1 PF0/IN0
A/D
P O R T C ) ( 8
8 bit Up/Down Counter 2 ch 8 bit 3 output D/A converter I 2C Interface 1 ch
P O R T F ( ) 5
Free Run Timer Input Capture
External Interrupt 16 ch
D A ( ) 3
DA2 DA1 DA0
19
MB91F155/MB91154
s CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory space. * Direct addressing area The following area in the address space is used for I/O. This area is called direct addressing area and an operand address can be specified directly in an instruction. The direct addressing area varies with the data size to be accessed as follows : byte data access : 0-0FFH half word data access : 0-1FFH word data access : 0-3FFH
2. Memory Map
* MB91F155 memory space
External ROMexternal bus mode 0000 0000H I/O 0000 0400H I/O 0000 0800H Not accessible 0000 1000H 32 KB internal RAM 0000 9000H 32 KB internal RAM 32 KB internal RAM Not accessible Not accessible I/O I/O I/O I/O Internal ROMexternal bus mode Single-chip mode Direct addressing area I/O map reference
Not accessible
Not accessible
Not accessible
0001 0000H External area Not accessible
0001 0000H
0008 0000H 2 KB internal RAM External area 510 KB internal ROM External area 01FF FFFFH Not accessible FFFF FFFFH Not accessible FFFF FFFFH Not accessible 510 KB internal ROM 0010 0000H 2 KB internal RAM 0008 0800H
Note : External areas are not accessible in single-chip mode.
20
MB91F155/MB91154
* MB91154 Memory Space
External ROMexternal bus mode 0000 0000H I/O 0000 0400H I/O 0000 0800H Not accessible 0000 1000H 20 KB internal RAM 0000 6000H 20 KB internal RAM 20 KB internal RAM Not accessible Not accessible I/O I/O I/O I/O Internal ROMexternal bus mode Single-chip mode Direct addressing area I/O map references
Not accessible
Not accessible
Not accessible
0001 0000H External area Not accessible
0001 0000H
0008 0000H 2 KB internal RAM 2 KB internal RAM 0008 0800H External area Not accessible 384 KB internal ROM External area 01FF FFFFH Not accessible FFFF FFFFH Not accessible FFFF FFFFH Not accessible Not accessible 000A 0000H 384 KB internal ROM 0010 0000H
Note : External areas are not accessible in single-chip mode.
21
MB91F155/MB91154
3. Registers
The family of FR microcontrollers has two types of registers : the registers residing in the CPU which are dedicated to applications and the general-purpose registers residing in the memory. * Dedicated registers : Program counter (PC) Program status (PS) Tablebase register (TBR)
: A 32-bit register to indicate the location where an instructions is stored. : A 32-bit register to store a register pointer or a condition code. : Holds the vector table lead address used when EIT (exceptions/interrupt/ trap) is processed. Return pointer (RP) : Holds the address to return from a subroutine to. System stack pointer (SSP) : Points to the system stack space. User stack pointer (USP) : Points to the user stack space. Multiplication and division result register (MDH/MDL) : A 32-bit multiplication and division register.
32 bit PC
Initial value Program counter Program status Tablebase register Return pointer System stack pointer User stack pointer 000F FC00H XXXX XXXXH (Undefined) 0000 0000H XXXX XXXXH (Undefined) XXXX XXXXH (Undefined) XXXX XXXXH (Undefined) XXXX XXXXH (Undefined)
PS
TBR
RP
SSP
USP
MDH MDL
Multiplication and division register
* Program status (PS) The PS register holds program status and is further divided into three registers which are a Condition Code Register (CCR) , a System condition Code Register (SCR) , and an Interrupt Level Mask register (ILM) .
31 PS
20
19
18
17
16
10 D1
9 D0 SCR
8 T
7
6
5 S
4 I
3 N
2 Z
1 V
0 C
ILM4 ILM3 ILM2 ILM1 ILM0 ILM
CCR
22
MB91F155/MB91154
* Condition Code Register (CCR) S flag : Designates the stack pointer for use as R15. I flag : Controls enabling and disabling of user interrupt requests. N flag : Indicates the sign when arithmetic operation results are considered to be an integer represented by 2's complement. Z flag : Indicates if arithmetic results were "0." V flag : Considers the operand used for an arithmetic operation to be an integer represented by 2's complement and indicates if the operation resulted in an overflow. C flag : Indicates whether or not an arithmetic operation resulted in a carry or a borrow from the most significant bit. * System condition Code Register (SCR) T flag : Designates whether or not to enable step trace trap. * Interrupt Level Mask register (ILM) ILM4 to ILM0 : Holds an interrupt level mask value to be used for level masking. An interrupt request is accepted only if the corresponding interrupt level among interrupt requests input to the CPU is higher than the value indicated by the ILM register. ILM4 0 0 1 ILM3 0 1 1 ILM2 0 0 1 ILM1 0 0 1 ILM0 0 0 1 Interrupt level 0 15 31 Lower High-Low Higher
23
MB91F155/MB91154
s GENERAL-PURPOSE REGISTERS
General-purpose registers are CPU registers R0 through R15 and used as accumulators during various operations and as memory access pointers (fields indicating addresses) . * Register Bank Configuration
32 bit
Initial value XXXX XXXXH
R0 R1
R12 R13 R14 R15
AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer)
XXXX XXXXH 0000 0000H
Of the 16 general-purpose registers, the following registers are assumed for specific applications. For this reason, some instructions are enhanced. R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP) Initial values to which R0 through R14 are reset are not defined. The initial value of R15 is 0000 0000H (the SSP value) .
24
MB91F155/MB91154
s SETTING MODE
1. Mode Pins
As shown in Table 1 three pins, MD2, 1, and 0 are used to indicate an operation. Table 1 Mode pins and set modes Mode pin Reset vector External data Mode name access area bus width MD2 MD1 MD0 0 0 0 0 1 0 0 1 1 0 1 0 1 External vector mode 0 External vector mode 1 External vector mode 2 External vector mode External External External Internal 8 bits 16 bits 32 bits (Mode register) External ROM bus mode Not available on this product type Single-chip mode Not available
2. Mode Data
The data which the CPU writes to "0000 07FFH" after reset is called mode data. It is the mode register (MODR) that exists at "0000 07FFH." Once a mode is set in this register, operations will take place in that mode. The mode register can be written only once after reset. The mode specified in the register is enabled immediately after it is written. MODR Address : 0000 07FFH

M1
M0
Initial value Access XXXXXXXX W
Bus mode setting bits
W: Write only, X: Undefined [bits 7 and 6] : M1, M0 These are bus mode setting bits. Specify the bus mode to be set to after writing to the mode register. M1 M0 Function Remarks 0 0 1 1 [bits 5 to 0] : These bits are reserved for the system. "0" should be written to these bits at all times. 0 1 0 1 Single-chip mode Internal ROM-external bus mode External ROM-external bus mode Setting not allowed
25
MB91F155/MB91154
[Precautions When Writing to the MODR] Before writing to the MODR, be sure to set AMD0 through 5 and determine the bus width in each CS (Chip Select) area. The MODR does not have bus width setting bits. The bus width value set with mode pins MD2 through 0 is enabled before writing to the MODR and the bus width value set with BW1 and 0 of AMD0 through 5 is enabled after writing to the MODR. For example, the external reset vector is normally executed with area 0 (the area where CS0 is active) and the bus width at that time is determined by pins MD 2 through 0. Suppose that the bus width is set to 32 or 16 bits in MD2 though 0 but no value is specified in AMD 0. If the MODR is written in this state, area 0 then switches to 8-bit bus mode and operates the bus since the initial bus width in AMD0 is set to 8 bits. This causes a malfunction. In order to prevent this type of problem, AMD0 through 5 must always be set before writing to the MODR.
Writing to the MODR. RST (Reset) Designated bus width : MD2,1,0 AMD0 to AMD5 BW1, 0
26
MB91F155/MB91154
s I/O MAP
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H SSR0 (R, R/W) 00001000 SSR1 (R, R/W) 00001000 SSR2 (R, R/W) 00001000 SSR3 (R, R/W) 00001000 PDRF (R/W) - - - XXXXX PDRJ (R/W) - - - - - - 11 SIDR0/SODR0 (R, W) XXXXXXXX SIDR1/SODR1 (R, W) XXXXXXXX SIDR2/SODR2 (R, W) XXXXXXXX SIDR3/SODR3 (R, W) XXXXXXXX PDRE (R/W) XXXXXXXX PDRI (R/W) - - XXXXXX Register +0 PDR3 (R/W) XXXXXXXX +1 PDR2 (R/W) XXXXXXXX PDR6 (R/W) XXXXXXXX PDRD (R/W) XXXXXXXX PDRH (R/W) - - XXXXXX PDRL (R/W) XXXXXXXX SCR0 (R/W, W) 00000100 SCR1 (R/W, W) 00000100 SCR2 (R/W, W) 00000100 SCR3 (R/W, W) 00000100 PDRC (R/W) XXXXXXXX PDRG (R/W) - - XXXXXX PDRK (R/W) XXXXXXXX SMR0 (R/W) 00000 - 00 SMR1 (R/W) 00000 - 00 SMR2 (R/W) 00000 - 00 SMR3 (R/W) 00000 - 00 UART0 PDR5 (R/W) XXXXXXXX +2 PDR4 (R/W) XXXXXXXX PDR8 (R/W) - XXXXXXX Port Data Register +3 Block
00001CH
000020H
UART1
000024H
UART2
000028H
UART3
00002CH 000030H 000034H 000038H 00003CH 000040H
TMRLR0 (W) XXXXXXXX XXXXXXXX TMRLR1 (W) XXXXXXXX XXXXXXXX TMRLR2 (W) XXXXXXXX XXXXXXXX
TMR0 (R) XXXXXXXX XXXXXXXX TMCSR0 (R/W) - - - - 0000 00000000 TMR1 (R) XXXXXXXX XXXXXXXX TMCSR1 (R/W) - - - - 0000 00000000 TMR2 (R) XXXXXXXX XXXXXXXX TMCSR2 (R/W) - - - - 0000 00000000
Reload Timer 0
Reload Timer 1
Reload Timer 2
(Continued)
27
MB91F155/MB91154
Address 000044H 000048H 00004CH 000050H 000054H to 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H RCR1 (W) 00000000 CCRH0 (R/W) 00000000 CCRH1 (R/W) - 0000000 CDCR1 (R/W) 0 - - - 0000 CDCR3 (R/W) 0 - - - 0000 TMRLR3 (W) XXXXXXXX XXXXXXXX
Register TMR3 (R) XXXXXXXX XXXXXXXX TMCSR3 (R/W) - - - - 0000 00000000 CDCR0 (R/W) 0 - - - 0000 CDCR2 (R/W) 0 - - - 0000 RCR0 (W) 00000000 CCRL0 (R/W, W) - 000X000 CCRL1 (R/W, W) - 000X000 UDCR1 (R) 00000000 UDCR0 (R) 00000000 CSR0 (R/W, R) 00000000 CSR1 (R/W, R) 00000000
Block
Reload Timer 3
Communications prescaler 1
Reserved
8/16 bit U/D Counter
IPCP1 (R) XXXXXXXX XXXXXXXX IPCP3 (R) XXXXXXXX XXXXXXXX ICS23 (R/W) 00000000
IPCP0 (R) XXXXXXXX XXXXXXXX IPCP2 (R) XXXXXXXX XXXXXXXX ICS01 (R/W) 00000000 16 bit ICU
OCCP1 (R/W) XXXXXXXX XXXXXXXX OCCP3 (R/W) XXXXXXXX XXXXXXXX OCCP5 (R/W) XXXXXXXX XXXXXXXX OCCP7 (R/W) XXXXXXXX XXXXXXXX OCS2, 3 (R/W) XXX00000 0000XX00 OCS6, 7 (R/W) XXX00000 0000XX00 TCDT (R/W) 00000000 00000000 STPR0 (R/W) 0000 - - - STPR1 (R/W) 00000000
OCCP0 (R/W) XXXXXXXX XXXXXXXX OCCP2 (R/W) XXXXXXXX XXXXXXXX OCCP4 (R/W) XXXXXXXX XXXXXXXX OCCP6 (R/W) XXXXXXXX XXXXXXXX OCS0, 1 (R/W) XXX00000 0000XX00 OCS4, 5 (R/W) XXX00000 0000XX00 TCCS (R/W) 0 - - - - - - - 00000000 STPR2 (R/W) 000000 - GCN2 (R/W) 00000000 16 bit Freerun Timer Stop Register 0, 1, 2 PPG ctl
16 bit OCU
GCN1 (R/W) 00110010 00010000
(Continued)
28
MB91F155/MB91154
Address 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H to 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH to 0000F0H PTMR0 (R) 11111111 11111111 PDUT0 (W) XXXXXXXX XXXXXXXX PTMR1 (R) 11111111 11111111 PDUT1 (W) XXXXXXXX XXXXXXXX PTMR2 (R) 11111111 11111111 PDUT2 (W) XXXXXXXX XXXXXXXX PTMR3 (R) 11111111 11111111 PDUT3 (W) XXXXXXXX XXXXXXXX PTMR4 (R) 11111111 11111111 PDUT4 (W) XXXXXXXX XXXXXXXX PTMR5 (R) 11111111 11111111 PDUT5 (W) XXXXXXXX XXXXXXXX EIRR0 (R/W) 00000000
Register PCSR0 (W) XXXXXXXX XXXXXXXX PCNH0 (R/W) 0000000 PCNL0 (R/W) 00000000
Block
PPG0
PCSR1 (W) XXXXXXXX XXXXXXXX PCNH1 (R/W) 0000000 PCNL1 (R/W) 00000000
PPG1
PCSR2 (W) XXXXXXXX XXXXXXXX PCNH2 (R/W) 0000000 PCNL2 (R/W) 00000000
PPG2
PCSR3 (W) XXXXXXXX XXXXXXXX PCNH3 (R/W) 0000000 PCNL3 (R/W) 00000000
PPG3
PCSR4 (W) XXXXXXXX XXXXXXXX PCNH4 (R/W) 0000000 PCNL4 (R/W) 00000000
PPG4
PCSR5 (W) XXXXXXXX XXXXXXXX PCNH5 (R/W) 0000000 EIRR1 (R/W) 00000000 PCNL5 (R/W) 00000000 ENIR1 (R/W) 00000000
PPG5
ENIR0 (R/W) 00000000
ELVR0 (R/W) 00000000 00000000 DACR2 (R/W) -------0 DADR2 (R/W) XXXXXXXX
ELVR1 (R/W) 00000000 00000000
Ext int
Reserved DACR1 (R/W) -------0 DADR1 (R/W) XXXXXXXX ADCS1 (R/W) 00000000 DACR0 (R/W) -------0 DADR0 (R/W) XXXXXXXX ADCS0 (R/W) 00000000 AICK (R/W) 00000000
D/A Converter
ADCR (R, W) 00101- XX XXXXXXXX
A/D Converter (Sequential type) Analog Input Control
Reserved
(Continued)
29
MB91F155/MB91154
Address 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H to 00011CH 000120H 000124H 000128H to 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H to 0003ECH CAC (R/W) 00000000 CA4 (R/W) - - - XXXXX IBCR (R/W) 00000000 IBSR (R) 00000000 PCRI (R/W) - - 000000 OCRI (R/W) - - 000000 DDRF (R/W) - - - 00000
Register PCRH (R/W) - - 000000 OCRH (R/W) - - 000000 DDRE (R/W) 00000000 DDRI (R/W) - 0000000 DDRD (R/W) 00000000 DDRH (R/W) - - 000000 DDRL (R/W) 00000000 IADR (R/W) - XXXXXXX DPDP (R/W) - - - - - - - - - - - - - - - - - - - - - - - - - 0000000 DACSR (R/W) 00000000 00000000 00000000 00000000 DATCR (R/W) XXXXXXXX XXXX0000 XXXX0000 XXXX0000 CA1 (R/W) - - XXXXXX CA5 (R/W) - - - - - XXX CAS (R/W) 0------0 CA2 (R/W) - - XXXXXX CA6 (R/W) - - - - XXXX CA3 (R/W) - - - XXXXX CA7 (R/W) - XXXXXXX ICCR (R/W) - - 0XXXXX PCRD (R/W) 00000000 DDRC (R/W) 00000000 DDRG (R/W) - - 000000 DDRK (R/W) 00000000 PCRC (R/W) 00000000
Block Pull Up Control Opendrain Control
Data Direction Register
Reserved
IDAR (R/W) XXXXXXXX
I2C Interface
Reserved
DMAC
Calendar
Reserved Calendar
Reserved
(Continued)
30
MB91F155/MB91154
Address 0003F0H 0003E4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH 000430H 000434H to 00047CH 000480H RSRR/WTCR (R, W) 1-XXX-00 GCR (R/W, R) 110011-1
Register BSD0 (W) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 (R/W) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC (W) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR (R) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICR00 (R/W) - - - - 1111 ICR04 (R/W) - - - - 1111 ICR08 (R/W) - - - - 1111 ICR12 (R/W) - - - - 1111 ICR16 (R/W) - - - - 1111 ICR20 (R/W) - - - - 1111 ICR24 (R/W) - - - - 1111 ICR28 (R/W) - - - - 1111 ICR32 (R/W) - - - - 1111 ICR36 (R/W) - - - - 1111 ICR40 (R/W) - - - - 1111 ICR44 (R/W) - - - - 1111 DICR (R/W) -------0 ICR01 (R/W) - - - - 1111 ICR05 (R/W) - - - - 1111 ICR09 (R/W) - - - - 1111 ICR13 (R/W) - - - - 1111 ICR17 (R/W) - - - - 1111 ICR21 (R/W) - - - - 1111 ICR25 (R/W) - - - - 1111 ICR29 (R/W) - - - - 1111 ICR33 (R/W) - - - - 1111 ICR37 (R/W) - - - - 1111 ICR41 (R/W) - - - - 1111 ICR45 (R/W) - - - - 1111 HRCL (R/W) - - - - 1111 STCR (R/W, W) 000111- WPR (W) XXXXXXXX PDRR (R/W) - - - - 0000 CTBR (W) XXXXXXXX ICR02 (R/W) - - - - 1111 ICR06 (R/W) - - - - 1111 ICR10 (R/W) - - - - 1111 ICR14 (R/W) - - - - 1111 ICR18 (R/W) - - - - 1111 ICR22 (R/W) - - - - 1111 ICR26 (R/W) - - - - 1111 ICR30 (R/W) - - - - 1111 ICR34 (R/W) - - - - 1111 ICR38 (R/W) - - - - 1111 ICR42 (R/W) - - - - 1111 ICR46 (R/W) - - - - 1111 ICR03 (R/W) - - - - 1111 ICR07 (R/W) - - - - 1111 ICR11 (R/W) - - - - 1111 ICR15 (R/W) - - - - 1111 ICR19 (R/W) - - - - 1111 ICR23 (R/W) - - - - 1111 ICR27 (R/W) - - - - 1111 ICR31 (R/W) - - - - 1111 ICR35 (R/W) - - - - 1111 ICR39 (R/W) - - - - 1111 ICR43 (R/W) - - - - 1111 ICR47 (R/W) - - - - 1111
Block
Bit Search Module
Interrupt Control unit
Delay int
Reserved
Clock Control unit
000484H
(Continued)
31
MB91F155/MB91154
(Continued) Address
000488H 00048CH to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH 000630H 000634H to 0007BCH 0007C0H 0007C4H 0007C8H to 0007F8H FLCR (R/W, R) 000X0000 FWTC (R/W, W) - - - - - 000 PCR6 (R/W) 00000000 FLASH Control Reserved DDR3 (W) 00000000 DDR2 (W) 00000000 DDR6 (W) 00000000 ASR1 (W) 00000000 00000001 ASR2 (W) 00000000 00000010 ASR3 (W) 00000000 00000011 ASR4 (W) 00000000 00000100 ASR5 (W) 00000000 00000101 AMD0 (R/W) - - - 00111 AMD5 (R/W) 0 - - 00000 EPCR0 (W) - - - - 1100 -1- - - - - AMD1 (R/W) 0 - - 00000 PTCR (R/W) 00XX0XXX DDR5 (W) 00000000 DDR4 (W) 00000000 DDR8 (W) - 0000000 AMR1 (W) 00000000 00000000 AMR2 (W) 00000000 00000000 AMR3 (W) 00000000 00000000 AMR4 (W) 00000000 00000000 AMR5 (W) 00000000 00000000 AMD32 (R/W) 00000000 EPCR1 (W) - - - - - - - - 11111111 Reserved Pull Up Control AMD4 (R/W) 0 - - 00000 Data Direction Register
Register
Block PLL Control
Reserved
T-unit
Reserved
32
MB91F155/MB91154
Address 0007FCH Register LER (W) - - - - - 000 MODR (W) XXXXXXXX Block Little Endian Register Mode Register
Note : Do not execute RMW instructions on registers having a write-only bit. RMW instructions (RMW : Read Modify Write) AND Rj, @Ri OR Rj, @Ri EOR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri EORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri EORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BEORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri BEORH #u4, @Ri Data is undefined in "Reserved" or () areas. ( ): R/W: R: W: : X: Access Read/Write enabled Read only Write only Not in use Undefined
33
MB91F155/MB91154
s INTERRUPT FACTORS AND ASSIGNMENT OF INTERRUPT VECTORS AND RESISTERS
Factor Reset Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Undefined instruction exception Reserved for the system External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 External interrupts 8 - 15 Reserved for the system UART0 (receiving complete) UART1 (receiving complete) UART2 (receiving complete) UART3 (receiving complete) Reserved for the system UART0 (sending complete) UART1 (sending complete) UART2 (sending complete) Interrupt No. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Hex. 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 Interrupt level ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR10 ICR11 ICR12 ICR13 ICR15 ICR16 ICR17 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H Default TBR address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H
(Continued)
34
MB91F155/MB91154
Factor UART3 (sending complete) IC DMAC (End, Error) Reload timer 0 Reload timer 1 Reload timer 2 Reload timer 3 A/D (sequential type) PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 U/Dcounter 0 (compare/underflow, overflow, up-down inversion) U/Dcounter 1 (compare/underflow, overflow, up-down inversion ICU0 (Read) ICU1 (Read) ICU2 (Read) ICU3 (Read) OCU0 (Match) OCU1 (Match) OCU2 (Match) OCU3 (Match) OCU4/5 (Match) OCU6/7 (Match) Reserved for the system 16-bit free-run timer Delay interrupt factor bit
2
Interrupt No. Decimal 34 35 36 37 38 39 40 42 43 44 45 46 47 48 49 Hex. 22 23 24 25 26 27 28 2A 2B 2C 2D 2E 2F 30 31
Interrupt level ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33
Offset 374H 370H 36CH 368H 364H 360H 35CH 354H 350H 34CH 348H 344H 340H 33CH 338H
Default TBR address 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H
50 51 52 53 54 55 56 57 58 59 60 61 62 63
32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR46 ICR47
334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H
000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H
(Continued)
35
MB91F155/MB91154
(Continued)
Factor Reserved for the system (used by REALOS*) Reserved for the system (used by REALOS*) Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Used with the INT instruction Interrupt No. Decimal 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 Hex. 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Offset 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H Default TBR address 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H
* : REALOS/FR uses 0X40 and 0X41 interrupts for system codes.
36
MB91F155/MB91154
s PERIPHERAL RESOURCES
1. I/O Port
(1) Port Block Diagram This LSI is available as an I/O port when the resource associated with each pin is set not to use a pin for input/ output. The pin level is read from the port (PDR) when it is set for input. When the port is set for output, the value in the data register is read. The same also applies to reload by read modify write. When switching from input to output, output data is set in the data register beforehand. However, if a read modify write instruction (such as bit set) is used at that time, keep in mind that it is the input data from the pin that is read, not the latch value of the data register. * Basic I/O Port
Data bus 0 Resource input
1 PDR read 0 PDR Resource output 1 Resource output allowed DDR PDR : Port Data Register DDR : Data Direction Register pin
Figure PORT-1 Basic port block The I/O port consists of the PDR (Port Data Register) and the DDR (Data Direction Register) . In input mode (DDR = "0") PDR read : Reads the level of the corresponding external pin. PDR write : Writes the set value to the PDR. In output mode (DDR = "1") PDR read : Reads the PDR value. PDR write : Outputs the PDR value to the corresponding external pin. Notes: AIC controls switching between the resource and port of the analog pin (A/D) . AICK (Analog Input Control register on port-K) The register controls whether port K should be used for analog input or as a general-purpose port. 0 : General-purpose port 1 : Analog input (A/D)
37
MB91F155/MB91154
* I/O Port (attached with a pullup resistor)
Data bus 0 Resource input
1 PDR read 0 PDR Resource output 1 Resource output allowed DDR pin
PCR PDR : Port Data Register DDR : Data Direction Register PCR : Pull-up Control Register
Figure PORT-2 Port block attached with a pullup resistor Notes : * Pullup resistor control register (PCR) R/W Controls turning the pullup resistor on/off. 0 : Pullup resistor disabled 1 : Pullup resistor enabled * In stop mode priority is also given to the setting of the pullup resistor control register. * This function is not available when a relevant pin is in use as an external bus pin. Do not write "1" to this register.
38
MB91F155/MB91154
* I/O Port (attached with the open drain output function and a pullup resistor)
Data bus 0 Resource input
1 PDR read 0 PDR Resource output Resource output allowed pin
1
DDR
ODCR
PCR PDR : Port Data Register DDR : Data Direction Register ODCR : OpenDrain Control Register PCR : Pull-up Control Register
Figure PORT-3 Port block attached with the open drain output function and a pullup resistor Notes : * Pullup resistor setup register (PCR) R/W Controls turning the pullup resistor on/off. 0 : Pullup resistor disabled 1 : Pullup resistor enabled * Open drain control register (ODCR) R/W Controls open drain in output mode. 0 : Standard output port during output mode 1 : Open-drain output port during output mode This register has no significance in input mode (output Hi-Z) . Input/output mode is determined by the direction register (DDR) . * Priority is also given to the setting of the pullup resistor control register in stop mode. * When a relevant pin is used as an external bus pin, neither function is available. Do not write "1" to either register.
39
MB91F155/MB91154
* I/O Port (open drain)
Data bus RMW Resource output RMW = 0 Resource input
RMW = 1 PDR read pin
PDR
PDR : Port Data Register
Figure PORT-4 Port block attached with a pullup resistor Notes : * When using as an input port or for resource input, set the PDR and resource output to "1." * During read by RMW, it is the PDR value that is read, not the pin value.
40
MB91F155/MB91154
(2) Register Descriptions * Port Data Register (PDR) PDR2 7 Address : 000001H PDR3 Address : 000000H PDR4 Address : 000007H PDR5 Address : 000006H PDR6 Address : 000005H PDR8 Address : 00000BH PDRC Address : 000013H PDRD Address : 000012H PDRE Address : 000011H PDRF Address : 000010H PDRG Address : 000017H PDRH Address : 000016H PDRI Address : 000015H PDRJ Address : 000014H PDRK Address : 00001BH PDRL Address : 00001AH
P27 7 P37 7 P47 7 P57 7 P67 7 7 PC7 7 PD7 7 PE7 7 7 7 7 7 7 PK7 7 PL7
6 P26 6 P36 6 P46 6 P56 6 P66 6 P86 6 PC6 6 PD6 6 PE6 6 6 6 6 6 6 PK6 6 PL6
5 P25 5 P35 5 P45 5 P55 5 P65 5 P85 5 PC5 5 PD5 5 PE5 5 5 PG5 5 PH5 5 PI5 5 5 PK5 5 PL5
4 P24 4 P34 4 P44 4 P54 4 P64 4 P84 4 PC4 4 PD4 4 PE4 4 PF4 4 PG4 4 PH4 4 PI4 4 4 PK4 4 PL4
3 P23 3 P33 3 P43 3 P53 3 P63 3 P83 3 PC3 3 PD3 3 PE3 3 PF3 3 PG3 3 PH3 3 PI3 3 3 PK3 3 PL3
2 P22 2 P32 2 P42 2 P52 2 P62 2 P82 2 PC2 2 PD2 2 PE2 2 PF2 2 PG2 2 PH2 2 PI2 2 2 PK2 2 PL2
1 P21 1 P31 1 P41 1 P51 1 P61 1 P81 1 PC1 1 PD1 1 PE1 1 PF1 1 PG1 1 PH1 1 PI1 1 PJ1 1 PK1 1 PL1
0 P20 0 P30 0 P40 0 P50 0 P60 0 P80 0 PC0 0 PD0 0 PE0 0 PF0 0 PG0 0 PH0 0 PI0 0 PJ0 0 PK0 0 PL0
Initial value Access XXXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
Initial value Access - XXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
Initial value Access - - - XXXXXB R/W
Initial value Access - - XXXXXXB R/W
Initial value Access - - XXXXXXB R/W
Initial value Access - - XXXXXXB R/W
Initial value Access - - - - - - 11B R/W
Initial value Access XXXXXXXXB R/W
Initial value Access XXXXXXXXB R/W
PDR2 to PDRL are the I/O data registers of the I/O port. Input/output is controlled with corresponding DDR2 to DDRL. R/W: Read/Write enabled, X: Undefined, : Not in use 41
MB91F155/MB91154
* Data Direction Register (DDR) DDR2 7 6 Address : 000601H DDR3 Address : 000600H DDR4 Address : 000607H DDR5 Address : 000606H DDR6 Address : 000605H DDR8 Address : 00060BH DDRC Address : 0000FFH DDRD Address : 0000FEH DDRE Address : 0000FDH DDRF Address : 0000FCH DDRG Address : 000103H DDRH Address : 000102H DDRI Address : 000101H DDRK Address : 000107H DDRL Address : 000106H
P27 7 P37 7 P47 7 P57 7 P67 7 7 PC7 7 PD7 7 PE7 7 7 7 7 7 PK7 7 PL7 P26 6 P36 6 P46 6 P56 6 P66 6 P86 6 PC6 6 PD6 6 PE6 6 6 6 6 TEST 6 PK6 6 PL6
5 P25 5 P35 5 P45 5 P55 5 P65 5 P85 5 PC5 5 PD5 5 PE5 5 5 PG5 5 PH5 5 PI5 5 PK5 5 PL5
4 P24 4 P34 4 P44 4 P54 4 P64 4 P84 4 PC4 4 PD4 4 PE4 4 PF4 4 PG4 4 PH4 4 PI4 4 PK4 4 PL4
3 P23 3 P33 3 P43 3 P53 3 P63 3 P83 3 PC3 3 PD3 3 PE3 3 PF3 3 PG3 3 PH3 3 PI3 3 PK3 3 PL3
2 P22 2 P32 2 P42 2 P52 2 P62 2 P82 2 PC2 2 PD2 2 PE2 2 PF2 2 PG2 2 PH2 2 PI2 2 PK2 2 PL2
1 P21 1 P31 1 P41 1 P51 1 P61 1 P81 1 PC1 1 PD1 1 PE1 1 PF1 1 PG1 1 PH1 1 PI1 1 PK1 1 PL1
0 P20 0 P30 0 P40 0 P50 0 P60 0 P80 0 PC0 0 PD0 0 PE0 0 PF0 0 PG0 0 PH0 0 PI0 0 PK0 0 PL0
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access 00000000B W
Initial value Access - 0000000B W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access - - - 00000B R/W
Initial value Access - - 000000B R/W
Initial value Access - - 000000B R/W
Initial value Access - 0000000B R/W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
DDR2 to DDRL control the I/O direction of the I/O port by bit. DDR = 0 : Port input DDR = 1 : Port output Note : DDRI's bit 6 is a test bit. Be sure to write "0" to the bit. "0" is the value that is read. R/W: Read/Write enabled, W: Write only, : Not in use 42
MB91F155/MB91154
* Pull-up Control Register (PCR) PCR6 7 6 Address : 000631H PCRC Address : 0000F7H PCRD Address : 0000F6H PCRH Address : 0000F5H PCRI Address : 0000F4H
P67 7 PC7 7 PD7 7 7 P66 6 PC6 6 PD6 6 6
5 P65 5 PC5 5 PD5 5 PH5 5 PI5
4 P64 4 PC4 4 PD4 4 PH4 4 PI4
3 P63 3 PC3 3 PD3 3 PH3 3 PI3
2 P62 2 PC2 2 PD2 2 PH2 2 PI2
1 P61 1 PC1 1 PD1 1 PH1 1 PI1
0 P60 0 PC0 0 PD0 0 PH0 0 PI0
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access 00000000B R/W
Initial value Access - - 000000B R/W
Initial value Access - - 000000B R/W
PCR6 to PCRI control the pullup resistor when the corresponding I/O port is in input mode. PCR = 0 : Pullup resistor not available in input mode PCR = 1 : Pullup resistor available in input mode The register has no significance in output mode (a pullup resistor not available) .
* Open Drain Control Register (ODCR) DCRH 7 6 5 Address : 0000F9H OCRI Address : 0000F8H
7 6 PH5 5 PI5
4 PH4 4 PI4
3 PH3 3 PI3
2 PH2 2 PI2
1 PH1 1 PI1
0 PH0 0 PI0
Initial value Access - - 000000B R/W
Initial value Access - - 000000B R/W
OCRH to OCRI control open drain when the corresponding I/O port is in output mode. OCR = 0 : Standard output port during output mode OCR = 1 : Open drain output port during output mode The register has no significance in input mode (output Hi-z) . * Analog Input Control Register (AICR) AICK 7 6 5 Address : 0000EBH
PK7 PK6 PK5
4 PK4
3 PK3
2 PK2
1 PK1
0 PK0
Initial value Access 00000000B R/W
The AICK controls each pin of a corresponding I/O port as follows : AIC = 1 : Port input mode AIC = 0 : Analog input mode The register is reset to "0." R/W: Read/Write enabled, : Not in use
43
MB91F155/MB91154
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. * 8 channels * Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer * Transfer all through the area * Max. 65536 of transfer cycles * Interrupt function right after the transfer * Selectable for address transfer increase/decrease by the software * External transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each * Block Diagram
DREQ0 to DREQ2
3
Edge/level detection circuit
3
3 3 Sequencer 8
DACK0 to DACK2 EOP0 to EOP2 Interrupt request
Internal resource transfer request
5
Data buffer
Switcher
DPDP
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
44
Data bus
DACSR
MB91F155/MB91154
* Registers (DMAC internal registers)
Address 00000200H 00000201H 00000202H 00000203H 00000204H 00000205H 00000206H 00000207H 00000208H 00000209H 0000020AH 0000020BH bit 31 bit 16
DPDP
bit 0
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB (R/W) X0000000B 00000000B 00000000B 0 0 0 0 0 0 0 0 B (R/W) 00000000B XXXXXXXXB XXXX0000B XXXX0000B (R/W) XXXX0000B
DACSR
DATCR
( ) : Access R/W : Read/Write enabled X : Undefined
* Register (DMA descriptor)
Address DPDP + 0H DPDP + 0CH bit 31 bit 0
DMA ch0 Descriptor DMA ch1 Descriptor
DPDP + 54H
DMA ch7 Descriptor
45
MB91F155/MB91154
3. UART
The UART is a serial I/O port for asynchronous (start and stop synchronization) communication or CLK synchronous communication. Its features are as follows : * Full-duplex double buffer * Capable of asynchronous (start and stop synchronization) and CLK synchronous communication. * Support for multiprocessor mode * Baud rate by a dedicated baud rate generator * Baud rate by an internal timer The baud rate can be set with a 16-bit reload timer. * Any baud rate can be set using an external clock. * Error detection function (parity, framing, and overrun) * NRZ-encoded transfer signals * DMA transfer can be invoked by interrupt.
46
MB91F155/MB91154
* Block Diagram
Control bus Receive interrupt signal #26 to 29 * Send interrupt signal #31 to 34 *
Dedicated baud rate generator Clock selector Receive clock Receiving control circuit Send clock
16-bit reload timer
(SCK0 to SCK3) Pin
Sending control circuit Sending start circuit Send bit counter Send parity counter
Start bit detection circuit Receive bit counter Receive parity counter
(SOT0 to SOT3) Pin
(SIN0 to SIN3) Pin Receive shift register Received status determination circuit Send shift register Sending start
SIDR0 to SIDR3
SODR0 to SODR3
Reception error Generated signals (to the CPU)
Internal data bus
SMR 0 - 3 registers
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR 0 - 3 registers
PEN P SBL CL A/D REC RXE TXE
SSR 0 - 3 registers
PE ORE FRE RDRF TDRE BDS RIE TIE
* : Interrupt numbers
47
MB91F155/MB91154
* Register List
Address 0000001EH 00000022H 00000026H 0000002AH 0000001FH 00000023H 00000027H 0000002BH 0000001CH 00000020H 00000024H 00000028H 0000001DH 00000021H 00000025H 00000029H
SSR0 SSR1 SSR2 SSR3 SIDR0/SODR0 SIDR1/SIDR1 SIDR2/SIDR2 SIDR3/SIDR3
bit 15
SCR0 SCR1 SCR2 SCR3
bit 8
bit 0
Initial value 00000100B 00000100B 00000100B 00000100B (R/W, W) (R/W, W) (R/W, W) (R/W, W) (R/W) (R/W) (R/W) (R/W) (R, R/W) (R, R/W) (R, R/W) (R, R/W)
SMR0 SMR1 SMR2 SMR3
00000-00B 00000-00B 00000-00B 00000-00B 00001000B 00001000B 00001000B 00001000B
XXXXXXXXB (R, W) XXXXXXXXB (R, W) XXXXXXXXB (R, W) XXXXXXXXB (R, W)
() R/W R W X
: Access : Read/Write enabled : Read only : Write only : Not in use : Undefined
48
MB91F155/MB91154
4. PPG Timer
The PPG timer can output highly accurate PWM waveforms efficiently. The MB91F155/MB91154 contains six PPG timer channels and its features are as follows : * Each channel consists of a 16-bit down counter, a 16-bit data register attached with a frequency setting buffer, a 16-bit compare register attached with a duty setting buffer, and a pin controller. * The count clock for the 16-bit down counter can be selected from the following four types : Internal clocks , /4, /16, and /64 * The counter value can be initialized by reset or counter borrow to "FFFFH." * PWM output (by channel) * DMA transfer can be invoked by interrupt. * Block Diagram (Entire configuration)
16-bit reload timer channel 0
TRG input PWM timer channel 0
PWM0
16-bit reload timer channel 1 General control register 1 (Factor selection) General control register 2 4
TRG input PWM timer channel 1
PWM1
TRG input PWM timer channel 2
PWM2
4 External TRG 0 to 3
TRG input PWM timer channel 3
PWM3
External TRG4
TRG input PWM timer channel 4
PWM4
External TRG5
TRG input PWM timer channel 5
PWM5
49
MB91F155/MB91154
* Block Diagram (for one channel)
PCSR
PDUT
Prescaler
1/1 1/4 1 / 16 1 / 64
ck
Load 16-bit down counter Start Borrow
cmp
PPG mask S Peripheral system clock Q
PWM output
R
Inverse bit Enable TRG input Edge detection Soft trigger Interrupt selection IRQ
50
MB91F155/MB91154
* Register List
Address 00000094H 00000095H 00000097H 00000098H 00000099H 0000009AH 0000009BH 0000009CH 0000009DH 0000009EH 0000009FH 000000A0H 000000A1H 000000A2H 000000A3H 000000A4H 000000A5H 000000A6H 000000A7H 000000A8H 000000A9H 000000AAH 000000ABH 000000ACH 000000ADH 000000AEH 000000AFH 000000B0H 000000B1H 000000B2H 000000B3H 000000B4H 000000B5H 000000B6H 000000B7H
PCNH3 PCNL3 PTMR3 PCSR3 PDUT3 PCNH2 PCNL2 PTMR2 PCSR2 PDUT2 PCNH1 PCNL1 PTMR1 PCSR1 PDUT1 PCNH0 PCNL0 PTMR0 PCSR0 PDUT0
bit 15
bit 8
GCN1
bit 0
Initial value 00110010B 0 0 0 1 0 0 0 0 B (R/W) 0 0 0 0 0 0 0 0 B (R/W) 11111111B (R ) 11111111B XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB XXXXXXXXB (W) 0 0 0 0 0 0 0 - B (R/W) 0 0 0 0 0 0 0 0 B (R/W) 11111111B 1 1 1 1 1 1 1 1 B (R) XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB (W) XXXXXXXXB 0 0 0 0 0 0 0 - B (R/W) 0 0 0 0 0 0 0 0 B (R/W) 11111111B 1 1 1 1 1 1 1 1 B (R) XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB 0 0 0 0 0 0 0 - B (R/W) 0 0 0 0 0 0 0 0 B (R/W) 11111111B (R) 11111111B XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB (W) XXXXXXXXB 0 0 0 0 0 0 0 - B (R/W) 0 0 0 0 0 0 0 0 B (R/W)
GCN2
(
) : Access R/W : Read/Write enabled R : Read only W : Write only : Not in use
X : Undefined
(Continued)
51
MB91F155/MB91154
(Continued)
Address 000000B8H 000000B9H 000000BAH 000000BBH 000000BCH 000000BDH 000000BEH 000000BFH 000000C0H 000000C1H 000000C2H 000000C3H 000000C4H 000000C5H 000000C6H 000000C7H
bit 15
bit 8
PTMR4 PCSR4 PDUT4 PCNH4 PCNL4 PTMR5 PCSR5 PDUT5 PCNH5 PCNL5
bit 0
Initial value 11111111B (R ) 11111111B XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB XXXXXXXXB (W) 0 0 0 0 0 0 0 - B (R/W) 0 0 0 0 0 0 0 0 B (R/W) 11111111B 1 1 1 1 1 1 1 1 B (R) XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB (W) XXXXXXXXB 0 0 0 0 0 0 0 - B (R/W) 0 0 0 0 0 0 0 0 B (R/W)
(
) : Access R : Read only : Not in use
R/W : Read/Write enabled W : Write only X : Undefined
52
MB91F155/MB91154
5. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating internal count clocks, and a control register. The input clock can be selected from three internal clock types (2/8/32 machine clock divisions) . DMA transfer can be invoked by interrupt. This product type contains this 16-bit reload timer for four channels. * Block Diagram
16 16-bit reload register 8 Reload RELD 16 16-bit down counter 2 GATE R bus CSL1 Clock selector CSL0 2 Retrigger IN CTL. EXCK Clear prescaler 3 MOD2 MOD1 Internal clocks MOD0 3 PWM (ch0, ch1) A/D (ch2) TRG CNTE UF OUTE OUTL OUT CTL. 2 INTE UF IRQ
21 23 25
53
MB91F155/MB91154
* Register List
Address 00000032H 00000033H 0000003AH 0000003BH 00000042H 00000043H 0000004AH 0000004BH 0000002EH 0000002FH 00000036H 00000037H 0000003EH 0000003FH 00000046H 00000047H 0000002CH 0000002DH 00000034H 00000035H 0000003CH 0000003DH 00000044H 00000045H bit 15
TMCSR0 TMCSR1 TMCSR2 TMCSR3 TMR0 TMR1 TMR2 TMR3 TMRLR0 TMRLR1 TMRLR2 TMRLR3
bit 0
Initial value ----0000B (R/W) 00000000B ----0000B (R/W) 00000000B ----0000B 0 0 0 0 0 0 0 0 B (R/W) ----0000B (R/W) 00000000B XXXXXXXXB (R) XXXXXXXXB XXXXXXXXB XXXXXXXXB (R) XXXXXXXXB XXXXXXXXB (R) XXXXXXXXB (R) XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB
( ) : Access R/W : Read/Write enabled R : Read only W : Write only : Not in use X : Undefined
54
MB91F155/MB91154
6. Bit Search Module
The module searches data written to the input register for "0" or "1" or a "change" and returns the detected bit position. * Block Diagram
Input latch
Address decoder
Detection mode
D bus
Changing one detection into data
Bit search circuit
Search results
* Register List
Address 000003F0H 000003F1H 000003F2H 000003F3H 000003F4H 000003F5H 000003F6H 000003F7H 000003F8H 000003F9H 000003FAH 000003FBH 000003FCH 000003FDH 000003FEH 000003FFH bit 31 bit 16
BSD0
bit 0
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (R/W) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (W) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (R) XXXXXXXXB
BSD1
BSDC
BSRR
(
) : Access W : Write only
R/W : Read/Write enabled X : Undefined
R : Read only
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MB91F155/MB91154
7. 8/10-bit A/D Converter (Sequential Conversion Type)
The A/D converter is a module that converts analog input voltage into a digital value. Its features are as follows : * A minimum conversion time of 5.0 s/ch. (Including sampling time at a 33 MHz machine clock) * Contains a sample and hold circuit. * Resolution : 10 or 8 bits selectable. * Selection of analog input from eight channels by program Single conversion mode : Selects and converts one channel. Continuous conversion mode : Converts a specified channel repeatedly. Stop and convert mode : Stops after converting one channel and stands by until invoked the next time. (Conversion invoking can be synchronized.) * DMA transfer can be invoked by interrupt. * Selection of an invoking factor from software, external pin trigger (falling edge) , and 16-bit reload timer (rising edge) . * Block Diagram
AVSS AVR MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
AVSS
D/A converter
Input circuit Comparator
Sequential compare register
Sample & hold circuit
Decoder
Data register ADCR
A/D control register 1 A/D control register 2 16-bit reload timer 2 External pin trigger ADCS1, 2 Operating clock Prescaler
56
R - BUS
MB91F155/MB91154
* Register List
bit 15 000000E4H 000000E5H 000000E6H 000000E7H 000000EBH
ADCS1 ADCS0 AICK ADCR
bit 0 0 0 1 0 1 - X X B (W, R) XXXXXXXXB (R) 0 0 0 0 0 0 0 0 B (R/W) 0 0 0 0 0 0 0 0 B (R/W) 0 0 0 0 0 0 0 0 B (R/W)
( ) : Access R/W : Read/Write enabled R : Read only W : Write only : Not in use X : Undefined
57
MB91F155/MB91154
8. Interrupt Controller
The interrupt controller accepts and arbitrates interrupts. * Block Diagram
INT0*2
IM
OR NMI*6
Priority determination 5 NMI processing 4 Level vector generation Level determination Request to withdraw HLDREQ 5 LEVEL4 to LEVEL0*4
HLDCAN*3
RI00 . . . RI47 (DLYIRQ)
ICR00 . . . . . ICR47 Vector determination 6
6
VCT5 to VCT0*5
DLYI*1
R bus
*1 : DLY1 represents the delay interrupt module (delay interrupt generator) . (For detailed information, see section 10, "Delay Interrupt Module." *2 : INT0 is a wake-up signal for the clock controller in sleep or stop mode. *3 : HLDCAN is a bus surrender request signal for bus masters except for the CPU. *4 : LEVEL 4 - 0 are interrupt level outputs. *5 : VCT 5 - 0 are interrupt vector outputs. *6 : This product type does not have the NMI function.
58
MB91F155/MB91154
* Register List
Address 00000400H 00000401H 00000402H 00000403H 00000404H 00000405H 00000406H 00000407H 00000408H 00000409H 0000040AH 0000040BH 0000040CH 0000040DH 0000040EH 0000040FH 00000410H 00000411H 00000412H 00000413H bit 7
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19
bit 0
Initial value - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W)
Address 00000414H 00000415H 00000416H 00000417H 00000418H 00000419H 0000041AH 0000041BH 0000041CH 0000041DH 0000041EH 0000041FH 00000420H 00000421H 00000422H 00000423H 00000424H 00000425H 00000426H 00000427H
bit 7
ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39
bit 0
Initial value - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W)
( ) : Access R/W : Read/Write enabled : Not in use
(Continued)
59
MB91F155/MB91154
(Continued)
Address 00000428H 00000429H 0000042AH 0000042BH 0000042CH 0000042DH 0000042EH 0000042FH 00000431H 00000430H
bit 7
ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 HRCL DICR
bit 0
Initial value - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - 1 1 1 1 B (R/W) - - - - - - - 0 B (R/W)
( ) : Access R/W : Read/Write enabled : Not in use
60
MB91F155/MB91154
9. External Interrupt
The external interrupt controller controls external interrupt requests input to INT pins 0 through 15. The level of requests to be detected can be selected from "H, " "L, " rising edge, and falling edge. * Block Diagram
16 Interrupt permission register 16 R bus 16
Interrupt request
Gate
Factor F/F
Edge detection circuit
INT0 to INT15
16
Interrupt factor register
32
Request level setting register
* Register List
Address 000000C8H 000000C9H 000000CAH 000000CBH 000000CCH 000000CDH 000000CEH 000000CFH Initial value 00000000B (R/W) 00000000B 00000000B (R/W) 00000000B 00000000B 0 0 0 0 0 0 0 0 B (R/W) 00000000B (R/W) 00000000B
bit 15
EIRR0 EIRR1
bit 8
ENIR0 ENIR1 ELVR0 ELVR1
bit 0
( ) : Access R/W : Read/Write enabled
10. Delay Interrupt Module
The delay interrupt is a module that generates task switching interrupts. The use of this module allows the software to generate/cancel interrupt requests to the CPU. For the block diagram of the delay interrupt module, see section 8, "Interrupt Controller." * Register List
Address 00000430H
bit 7
DICR
bit 0
Initial value -------0
B (R/W)
( ) : Access R/W : Read/Write enabled : Not in use 61
MB91F155/MB91154
11. Clock Generator (Low power consumption mechanism)
The clock generator is responsible for the following functions : * CPU clock generation (including the gear function) * Peripheral clock generation (including the gear function) * Reset generation and holding factors * Standby function (including hardware standby) * Contains PLL (multiplication circuit)
62
MB91F155/MB91154
* Block Diagram
[Gear controller] GCR register CPU gear Peripheral gear
1/2 X0 X1 Oscillator circuit PLL
M P X
Internal clock generating circuit
CPU Clock Internal bus clock Internal peripheral clock
[Stop/sleep controller] Internal interrupt Internal reset STCR register Stop state Sleep state CPU Hold request Reset generating F/F Internal reset
DMA request PDRR register Status transition control circuit
Power on detection circuit VCC
[Reset factor circuit]
R GND RST pin [Watchdog controller] WPR register Watchdog F/F CTBR register Timebase timer Count clock RSRR register
63
MB91F155/MB91154
* Register List
Address 00000480H 00000481H 00000482H 00000483H 00000484H 00000485H
GCR WPR PDRR CTBR
bit 15
RSRR/WTCH
bit 8
bit 0
Initial value 1-XXX-00B (R, W) (R/W, W) (R/W)
STCR
000111--B ----0000B
XXXXXXXXB (W) 110011-1B (R/W, R)
XXXXXXXXB (W)
( ) : Access R/W : Read/Write enabled R : Read only W : Write only : Not in use X : Undefined
64
MB91F155/MB91154
12. External Bus Interface
The external bus interface controls the interface between the external memory and the external I/O. Its features are as follows : * 24-bit (16 MB) address output * An 8/16-bit bus width can be set by chip select area. * Inserts an automatic and programmable memory wait (for seven cycles at maximum) . * Unused addresses/data pins are available as I/O ports. * Support for little endian mode * Use of a clock doubler, 33 MHz internal and 16.5 MHz external bus operations * Block Diagram
ADDRESS BUS
A-Out DATA BUS M U X
Write buffer
External DATA Bus
Switch
Read buffer
Switch DATA BLOCK ADDRESS BLOCK +1 or +2
Address buffer Inpage
Shifter
External Address Bus
4 ASR AMR
Comparator
CS0 to CS3
3 External pin controller
Controls all blocks.
RD WR0, WR1 BRQ BGRNT RDY CLK
Registers & Control
4
65
MB91F155/MB91154
* Register List
Address 0000060CH 0000060DH 0000060EH 0000060FH 00000610H 00000611H 00000612H 00000613H 00000614H 00000615H 00000616H 00000617H 00000618H 00000619H 0000061AH 0000061BH 0000061CH 0000061DH 0000061EH 0000061FH 00000620H 00000621H 00000622H 00000623H 00000624H 00000628H 00000629H 0000062AH 0000062BH 000007FEH 000007FFH
AMD5 EPCR0 EPCR1 LER MODR AMD0 AMD1 AMD32 AMD4 ASR5 AMR5 ASR4 AMR4 ASR3 AMR3 ASR2 AMR2
bit 31
ASR1
bit 16
bit 0
Initial value 00000000B 0 0 0 0 0 0 0 1 B (W) 00000000B (W) 00000000B 00000000B (W) 00000010B 00000000B (W) 00000000B 00000000B (W) 00000011B 00000000B (W) 00000000B 00000000B (W) 00000100B 0 0 0 0 0 0 0 0 B (W) 00000000B 00000000B (W) 00000101B 00000000B (W) 00000000B - - - 0 0 1 1 1 B (R/W) 0 - - 0 0 0 0 0 B (R/W) 0 0 0 0 0 0 0 0 B (R/W) 0 - - 0 0 0 0 0 B (R/W) 0 - - 0 0 0 0 0 B (R/W) ----1100B (W) -1111111B --------B (W) 11111111B - - - - - 0 0 0 B (W) XXXXXXXXB (W)
AMR1
( ) : Access R/W : Read/Write enabled W : Write only : Not in use X : Undefined
66
MB91F155/MB91154
13. Multifunction Timer
The multifunction timer unit consists of one 16-bit free-run timer, eight 16-bit output compare registers, four 16bit input capture registers, and six 16-bit PPG timer channels. By using this function 12 independent waveforms can be output based on the 16-bit free-run timer and the input pulse width and external clock cycle can also be measured. * Timer Components * 16-bit free-run timer ( x 1) The 16-bit free-run timer consists of a 16-bit up counter, a control register, a 16-bit compare clear register, and a prescaler. The output value of this counter is used as the basic time (base timer) for output compare and input capture. * Output compare ( x 8) The output compare consists of eight 16-bit compare registers, a compare output latch, and a control register. When the 16-bit free-run timer value agrees to the compare register value, the output level can be inverted and an interrupt can also be generated. * Input capture ( x 4) The input capture consists of capture registers corresponding to four independent external input pins and a control register. By detecting any edge of signals input from external input pins, the 16-bit free-run timer value can be held in the capture register and an interrupt can be generated at the same time. * 16-bit PPG timer ( x 6) See the section on the PPG Timer.
67
MB91F155/MB91154
* Block Diagram
Interrupt IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Divider Clock 16-bit free-run timer
16-bit compare clear register (Channel 6's compare register) Compare register 0/2/4
Compare circuit MS13 to 0 T CMOD Select T Q OC1/3/5 ICLR Q ICRE OC0/2/4
Interrupt
Compare circuit Compare register 1/3/5 R-BUS
Compare circuit
IOP1
IOP0
IOE1
IOE0 Interrupt Interrupt
Capture register 0/2
Edge detection
IN 0/2
EG11
EG10
EG01
EG00
Capture register 1/3
Edge detection
IN 1/3
ICP0
ICP1
ICE0
ICE1 Interrupt Interrupt
68
MB91F155/MB91154
* Register List
Address 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000071H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH
bit15 bit8 bit7 IPCP1 bit0
Initial value XXXXXXXXB ( R ) XXXXXXXXB ( R ) XXXXXXXXB ( R ) XXXXXXXXB ( R ) XXXXXXXXB ( R ) XXXXXXXXB ( R ) XXXXXXXXB ( R ) XXXXXXXXB ( R )
IPCP0
IPCP3
IPCP2
ICS23
00000000B ( R/W ) 00000000B ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXXXXXXXB ( R/W ) XXX00000B ( R/W ) 0000XX00B ( R/W ) XXX00000B ( R/W ) 0000XX00B ( R/W ) XXX00000B ( R/W ) 0000XX00B ( R/W ) XXX00000B ( R/W ) 0000XX00B ( R/W ) 00000000B ( R/W ) 00000000B ( R/W ) 0 - - - - - - - B ( R/W ) 00000000B ( R/W )
ICS01
OCCP1
OCCP0
OCCP3
OCCP2
OCCP5
OCCP4
OCCP7
OCCP6
OCS3,2
OCS1,0
OCS7,6
OCS5,4
TCDT
TCCS
(
) : Access R/W : Read/Write enabled R : Read only : Not in use
X : Undefined 69
MB91F155/MB91154
14. Calendar Macro * Backup RAM
This macro is a calendar macro with a basic clock of 32.768 kHz. The macro accomplishes clock functions including, year, month, date, hour, minutes, seconds, day of the week, and leap years. The macro counts the last two digits of calendar years 0 through 99. A backup RAM is also contained. * Block Diagram
VCC2 (for backup)
Oscillator Calendar circuit 32 kHz D BACKUP (for data protection) Bus controller b u s
Backup RAM
* Register List
Address Initial value
bit15 CAC
bit8
bit17 CA1
bit0
000210H 000211H 000212H 000213H 000214H 000215H 000216H 000217H 00021FH
00000000B ( R/W ) - - XXXXXXB ( R/W ) - - XXXXXXB ( R/W ) - - - XXXXXB ( R/W ) - - -XXXXXB ( R/W ) - - - - - XXXB ( R/W ) - - - - XXXXB ( R/W ) - XXXXXXXB ( R/W ) 0 - - - - - - 0B ( R/W )
CA2
CA3
CA4
CA5
CA6
CA7
CAS
( ) : Access R/W : Read/Write enabled : Not in use X : Undefined
70
MB91F155/MB91154
15. I2C Interface
The I2C interface is a serial I/O port that supports the Inter IC BUS and operates as a master/slave device on the I2C bus. * Features of the I2C Interface Contains one I2C interface channel. The interface has the following features : * Master/slave send and receive * Arbitration function * Clock synchronization function * Slave address/general call address detection function * Transfer direction detection function * Repeated generation and detection of start conditions * Bus error detection function * Register List * Bus control register (IBCR) Address bit 15 bit 14 0000-0120H BER BEIE
R/W R/W
bit 13 SCC R/W
bit 12 MSS R/W
bit 11 ACK R/W
bit 10 GCAA R/W
bit 9 INTE R/W
bit 8 INT R/W
Initial value 00000000B
* Bus status register (IBSR) Address bit 7 bit 6 0000-0121H BB RSC
R R
bit 5 AL R
bit 4 LRB R
bit 3 TR R
bit 2 AAS R
bit 1 GCA R
bit 0 FBT R
Initial value 00000000B
* Address register (IADR) Address bit 15 0000-0122H
bit 14 A6 R/W
bit 13 A5 R/W
bit 12 A4 R/W
bit 11 A3 R/W
bit 10 A2 R/W
bit 9 A1 R/W
bit 8 A0 R/W
Initial value - XXXXXXXB
* Clock control register (ICCR) Address bit 7 bit 6 0000-0123H

bit 5 EN R/W
bit 4 CS4 R/W
bit 3 CS3 R/W
bit 2 CS2 R/W
bit 1 CS1 R/W
bit 0 CS0 R/W
Initial value - - 0XXXXXB
* Data register (IDAR) Address bit 7 0000-0125H D7
R/W
bit 6 D6 R/W
bit 5 D5 R/W
bit 4 D4 R/W
bit 3 D3 R/W
bit 2 D2 R/W
bit 1 D1 R/W
bit 0 D0 R/W
Initial value XXXXXXXXB
R/W : Read/Write enabled, R: Read only, : Not in use, X: Undefined
71
MB91F155/MB91154
* Block Diagram
ICCR EN Clock division 1 5 6 7 8 ICCR CS4 CS3 R bus Clock division 2 CS2 CS1 CS0 IBSR BB RSC LRB TR FBT AL IBCR BER SDA BEIE Interrupt request INTE INT IBCR SCC MSS ACK permission ACK GC-ACK permission GCAA Start/stop condition detection Start Master End IRQ First Byte Arbitration lost detection Bus busy Repeat start Last Bit Send/Receive Start/stop condition detection Error Clock selection 2 Shift clock edge variation timing 2 4 8 16 32 64 128 256 Sync Shift clock generation Clock selection 1
I2C enable Peripheral clock
SCL
IDAR IBSR AAS GCA Slave Global call Slave address comparison
IADR
72
MB91F155/MB91154
16. FLASH Memory
The MB91F155 contains a 510-Kbyte (4 Mbits) flash memory of which the sectors can be erased all at once or sector by sector and that can be written with the FR-CPU by half word (16 bits) using a single 0.3 V power supply. The MB91F155 accomplishes the following functions by a combination of the flash memory macro and the FRCPU interface circuit : * Functions as the CPU program/data storage memory : When used as a ROM, the memory is accessible with a 32-bit bus width. Allows the CPU to read from/write to/erase the memory (automatic program algorithm*) . * Functions equivalent to the stand-alone MBM29LV400C flash memory product : Allows a ROM programmer to read from/write to/erase the memory (automatic program algorithm*) At this time, using the flash memory from the FR-CPU is described. For detailed information about using the flash memory from the ROM programmer, refer to the ROM programmer instruction manual. * : Automatic program algorithm = Embedded AlgorithmTM Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc. * Block Diagram
Rising edge detection
RDY/BUSY
Control signal generation
RESET BYTE OE
Flash memory 4 Mbit (510 K x 8/255 K x 16)
WE CE Bus control signals Interrupt requests FA18 - 0 DI15 - 0 DO31 - 0
INTE
RDYINT
RDY
WE
Address buffer CA18 - 0
Data buffer CD31 - 0
FR-C bus (instructions/data)
73
MB91F155/MB91154
* Memory Map Flash memory address mapping varies between FLASH memory mode and CPU mode. Mapping in each mode is shown next. Memory mapping in FLASH memory mode :
0FFFFFH
SA13 SA12 SA11
4M-FLASH memory image
SA10 SA9 SA8 SA7
07FFFFH
SA6 SA5 SA4 SA3 FLASH memory mode
010000H
SA2 SA1 SA0 ( SAn : sector address n )
000000H
Memory mapping in CPU mode :
0FFFFFH 0FFFFFH 0F8000H 0F4000H FLASH memory area 0F0000H 0E0000H
SA2 SA9 SA5 SA4 SA3 SA12 SA11 SA10
SA6
SA13
080800H RAM area 2 Kbytes 080000H
0C0000H
SA1 SA8
0A0000H
SA0 SA7 CPU mode
0007C0H 000000H
Status register
080800H 080000H
( SAn : sector address n )
74
MB91F155/MB91154
* Sector Address Table Sector address SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA0 SA1 SA2 SA3 SA4 SA5 SA6 Address range 080802, 3H to 09FFFE, FH (16 bits on LSB side) 0A0002, 3H to 0BFFFE, FH (16 bits on LSB side) 0C0002, 3H to 0DFFFE, FH (16 bits on LSB side) 0E0002, 3H to 0EFFFE, FH (16 bits on LSB side) 0F0002, 3H to 0F3FFE, FH (16 bits on LSB side) 0F4002, 3H to 0F7FFE, FH (16 bits on LSB side) 0F8002, 3H to 0FFFFE, FH (16 bits on LSB side) 080800, 1H to 09FFFC, DH (16 bits on MSB side) 0A0000, 1H to 0BFFFC, DH (16 bits on MSB side) 0C0000, 1H to 0DFFFC, DH (16 bits on MSB side) 0E0000, 1H to 0EFFFC, DH (16 bits on MSB side) 0F0000, 1H to 0F3FFC, DH (16 bits on MSB side) 0F4000, 1H to 0F7FFC, DH (16 bits on MSB side) 0F8000, 1H to 0FFFFE, FH (16 bits on MSB side) Corresponding bit positions bit15 to 0 bit15 to 0 bit15 to 0 bit15 to 0 bit15 to 0 bit15 to 0 bit15 to 0 bit31 to 16 bit31 to 16 bit31 to 16 bit31 to 16 bit31 to 16 bit31 to 16 bit31 to 16 Sector capacity 64 Kbyte 64 Kbyte 64 Kbyte 32 Kbyte 8 Kbyte 8 Kbyte 16 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 32 Kbyte 8 Kbyte 8 Kbyte 16 Kbyte
* Registers FLCR : Status register (CPU mode) This register indicates the FLASH memory operating status. The register controls interrupts to the CPU as well as writing to the FLASH memory. This register is accessible only in CPU mode. Do not access this register with read modify write instructions.
bit 7 bit 6 RDYINT R/W (0) bit 5 WE R/W (0) bit 4 RDY R (X) bit 3 (X) bit 2 (X) bit 1 (X) bit 0 LPM R/W (0)
0007C0H
INTE R/W (0)
R/W: Read/Write enabled, R: Read only, : Not in use, X: Undefined
FWTC : Wait register This register controls waiting for the FLASH memory in CPU mode. The register also controls accessing to read from the FLASH memory (33 MHz operations) at high speeds.
bit 7 bit 6 () bit 5 () bit 4 () bit 3 () bit 2 FACH W (0) bit 1 WTC1 R/W (0) bit 0 WTC0 R/W (0)
0007C4H
()
R/W: Read/Write enabled, W: Write only, : Not in use, X: Undefined
75
MB91F155/MB91154
17. 8-bit D/A Converter
This block is of an 8-bit resolution, R-2R D/A converter. The block contains three D/A converter channels and each D/A control register can control output independently. The D/A converter pin is a dedicated pin. * Block Diagram
R - BUS
DA27 DA20
DA17 DA10
DA07 DA00
DAVC DA27 DA17
DAVC DA07
DAVC
DA20
DA10
DA00
DAE2 Standby control
DAE1 Standby control
DAE0 Standby control
D/A output channel 2
D/A output channel 1
D/A output channel 0
76
MB91F155/MB91154
* Register List
bit
7 DA07
6 DA06
5 DA05
4 DA04
3 DA03
2 DA02
1 DA01
0 DA00
Initial value
DADR0 00000E3H
XXXXXXXXB ( R/W )
bit
15 DA17
14 DA16
13 DA15
12 DA14
11 DA13
10 DA12
9 DA11
8 DA10
DADR1 00000E2H
XXXXXXXXB ( R/W )
bit
23 DA27
22 DA26
21 DA25
20 DA24
19 DA23
18 DA22
17 DA21
16 DA20
DADR2 00000E1H
XXXXXXXXB ( R/W )
bit
7
6
5
4
3
2
1
0 DAE0
DACR0 00000DFH
- - - - - - - 0B ( R/W )
bit
15
14
13
12
11
10
9
8 DAE1
DACR1 00000DEH
- - - - - - - 0B ( R/W )
bit
23
22
21
20
19
18
17
16 DAE2
DACR2 00000DDH
- - - - - - - 0B ( R/W )
( ): Access, R/W: Read/Write enabled, : Not in use, X: Undefined
77
MB91F155/MB91154
18. 8/16-bit Up/Down Counters/Timers
This is the up/down counter/timer block consisting of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and their control circuits. The features of this module are as follows : * Capable of counting in the (0) d- (256) d range by the 8-bit count register. (In 16-bit x 1 operating mode, the register can count in the (0) d- (65535) d range.) * Four count modes to choose from by the count clock. * In timer mode the count clock can be selected from two internal clock types. * In up/down count mode an external pin input signal detection edge can be selected. * The phase-difference count mode is suitable for encoder counting, such as of motors. Rotation angles, rotating speeds, and so on can be counted accurately and easily by inputting the output of phases A, B, and Z. * Two types of function to choose from for the ZIN pin. (Enabled in all modes) * Equipped with compare and reload functions which can be used individually or in combination. When combined, these functions can count up/down at any width. * The immediately preceding count direction can be identified by the count direction flag. * Capable of individually controlling interrupt generation when comparison results match, at occurrence of reload (underflow) or overflow, or when the count direction changes.
78
MB91F155/MB91154
* Block Diagram * 8/16-bit Up/Down Counter/Timer (channel 0)
Data bus 8 bit CGE1 CGE0 C/GS RCR0 (Reload/compare register 0)
RCUT ZIN0 Edge/level detection
Reload control
UCRE
RLDE
UDCC
Counter clear 8 bit UDCR0 (Up/down count register 0) Carry CMPF
CES1 CMS1
CES0 CMS0 CITE
UDFF
OVFF
UDIE
AIN0 BIN0 Up/down count clock selection UDF1 UDF0 CDCF
Counter clock CFIE
Prescaler
CSTR Interrupt output
CLKS
79
MB91F155/MB91154
* 8/16-bit Up/Down Counter/Timer (channel 1)
Data bus 8 bit CGE1 CGE0 C/GS RCR1 (Reload/compare register 1)
RCUT ZIN1 Edge/level detection
Reload control
UCRE
RLDE
UDCC
Counter clear 8 bit UDCR1 (Up/down count register 1) CMPF
UDFF CMS1 CMS0 CES1 Carry AIN1 BIN1 Up/down count clock selection UDF1 UDF0 CDCF Counter clock CFIE CES0 M16E CITE UDIE
OVFF
Prescaler
CSTR Interrupt output
CLKS
80
MB91F155/MB91154
* Register List
bit 7 6 5 4 3 UDCR0 bit 15 14 13 12 11 UDCR1 bit 7 6 5 4 RCR0 bit 15 14 13 12 RCR1 bit 7 6 5 4 CSR0 bit 7 6 5 4 CSR1 bit 7 6 5 4 CCRL0 bit 7 6 5 4 CCRL1 bit 15 14 13 12 11 CCRH0 bit 15 14 13 12 11 CCRH1 10 9 8 10 9 8 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 11 10 9 8 3 2 1 0 10 9 8 2 1 0
Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value -000X000B (R/W, W) Initial value -000X000B (R/W, W) Initial value 00000000B Initial value -0000000B (R/W) (R/W) (R/W) (R/W) (W) (W) (R) (R)
Address : 00005FH
Address : 00005EH
Address : 00005DH
Address : 00005CH
Address : 000063H
Address : 000067H
Address : 000061H
Address : 000065H
Address : 000060H
Address : 000064H
( ): Access, R/W: Read/Write enabled, R: Read only, W: Write only, : Not in use, X: Undefined
81
MB91F155/MB91154
19. Peripheral STOP Control
This function can be used to stop the clock of unused resources in order to conserve more power. * Register List
Address bit7 STPR0 bit0 Initial value
000090H 000091H 000092H
0000 - - - - B ( R/W ) 00000000B ( R/W ) 000000 - - B ( R/W )
STPR1 STPR2
( ): Access, R/W: Read/Write enabled, : Not in use
82
MB91F155/MB91154
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 0 -55 Max. VSS + 3.6 VSS + 3.6 VSS + 3.6 VCC + 0.3 VSS + 5.5 AVCC + 0.3 VCC + 0.3 10 4 100 50 -10 -4 -50 -20 500 +70 +150 (VSS = AVSS = 0.0 V) Symbol VCC, VCC2 AVCC AVRH VI VI2 VIA VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Unit V V V V V V V mA mA mA mA mA mA mA mA mW C C *4 *4 *2 *3 *2 *3 *1 *1 Remarks
Parameter Power supply voltage Analog supply voltage Analog reference voltage Input voltage Input voltage (open drain port J) Analog pin input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
*1 : Take care not to exceed Vcc + 0.3 V when turning on the power, for example. Take care also to prevent AVcc from exceeding Vcc when turning on the power, for example. *2 : The maximum output current stipulates the peak value of a single concerned pin. *3 : The average output current stipulates the average current flowing through a single concerned pin over a period of 100 ms. *4 : The total average output current stipulates the average current flowing through all concerned pins over a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
83
MB91F155/MB91154
2. Recommended Operating Conditions
Value Min. 3.15 Power supply voltage Analog supply voltage Analog reference voltage Operating temperature VCC, VCC2 AVCC AVRH TA 2.0 VSS + 3.15 AVSS 0 Max. 3.6 3.6 VSS + 3.6 AVCC +70 V V V C
(VSS = AVSS = 0.0 V) Unit Remarks During normal operations. The RAM state is retained when stopped.
Parameter
Symbol
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
84
MB91F155/MB91154
3. DC Characteristics
(VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Pin name Condition Value Min. 0.65 x VCC 0.8 x VCC VSS - 0.3 VSS - 0.3 Typ. Max. VCC + 0.3 VCC + 0.3 0.25 x VCC 0.2 x VCC 0.4 50 TBD TBD TBD 5 0.4 VSS + 5.0 TBD TBD TBD Unit V V V V V V A V V k mA mA A During sleep mode When stopped Backup current when calendar is not in use (32 kHz stopped) Open drain Open drain Remarks
Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leakage current "L" level output voltage Output application voltage Pullup resistance
Symbol
VIH VIHS VIL VILS VOH VOL ILI VOL2 VD
Input except for hysteresis input pin* Hysteresis input pin* Input except for hysteresis input pin* Hysteresis input pin* Except for port J. Except for port J. Port J Port J
VCC = 3.15 V VCC - 0.5 IOH = 4.0 mA VCC = 3.15 V IOL = 4.0 mA VCC = 3.6 V, VSS RPULL RST, pullup pin ICC ICCS VCC VCC VCC
Power supply current
ICCH
ICCH2
VCC2
TBD
TBD
A
* : See "s I/O Circuit Type" in chapter 1.
(Continued)
85
MB91F155/MB91154
(Continued)
(VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Symbol Pin name Condition VCC = 3.3 V, 33 MHz VCC = 3.3 V, 33 MHz VCC = 3.3 V, TA = 25 C VCC = 3.3 V, TA = 25 C Value Min. Typ. 85 Max. 120 Unit Remarks
Parameter
ICC
VCC
External buss mA access available mA A During sleep mode When stopped Backup current when calendar is not in use (32 kHz stopped)
Power supply current (Products with an internal flash memory)
ICCS ICCH
VCC VCC
60 15
100 150
ICCH2
VCC2
0.1
1
A
Input capacity
CIN
Other than Vcc, Vss, AVcc, AVss, and AVRH
10
pF
86
MB91F155/MB91154
4. Flash Memory Erase and Programming Performance
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycle * : Ta = 25 C, VCC = 3.3 V Value Min. 10000 Typ. 1* 8* 2.1 * Max. 15 * 150 * 3600 * Unit s s s s cycle Remarks Excludes programming time prior to erasure Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead
87
MB91F155/MB91154
5. AC Characteristics
(1) Clock Timing Ratings Symbol (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Pin name Condition Value Min. Max. Unit Remarks Range in which self oscillation is allowed 10 Clock frequency (high speed and PLL in use) fC X0, X1 16.5 MHz Range in which self oscillation and the use of the PLL for external clock input are allowed Range in which exterMHz nal clocks can be input kHz 1600*4 10 33 25*3 33 33 1600*4 1600*4 1600*4 1000 ns % Self oscillation and external clocks
Parameter Clock frequency (high speed and self oscillation)
Clock frequency (High speed an 1/2 division input) Clock frequency (for the calendar macro) Clock cycle time Frequency regulation * (When the PLL is locked.) CPU system Internal operating clock frequency Bus system Peripheral system CPU system Internal operating clock cycle time Bus system Peripheral system
1
fCA tC f fCP fCPB X0A, X1A
10
18
32 30.3 0.625*4 0.625*4 0.625*4
One wait is set with the wait controller.
MHz Analog section excluded. *2 Analog section *2
fCPP
1 30.3 40*3 30.3 30.3
tCP tCPB
ns Analog section excluded. *2 section *2
tCPP
*1 : Frequency regulation is the maximum fluctuation from a set center frequency, represented in percentage, when locked to a multiple. *2 : The target analog section is the A/D. *3 : The maximum external bus operating frequency allowed is 25 MHz. *4 : The value when a minimum clock frequency of 10 MHz is input to X0 and half a division of the oscillator circuit and the 1/8 gear are in use.
88
MB91F155/MB91154
+
+
f =
|| fO
x100 (%)
Center frequency fO -
-
tC
PWH tcf
PWL tcr
VCC Operation assurance range Supply voltage (V) 3.6 fCPP
3.15
fCP
0.625 M Frequency (Hz)
33 M
89
MB91F155/MB91154
The relationship between the X0 input and the internal clock set with the CHC/CCK1/CCK0 bit of the GCR (Gear Control Register) is as shown next.
X0 input * Source oscillation x 1 (GCR CHC bit : 0) (a) Gear x 1 internal clock CCK1/0 : 00 (b) Gear x 1/2 internal clock CCK1/0 : 01 (c) Gear x 1/4 internal clock CCK1/0 : 10 (d) Gear x 1/8 internal clock CCK1/0 : 11 * Source oscillation x 1/2 (GCR CHC bit : 1) (a) Gear x 1 internal clock CCK1/0 : 00 (b) Gear x 1/2 internal clock CCK1/0 : 01 (c) Gear x 1/4 internal clock CCK1/0 : 10 (d) Gear x 1/8 internal clock CCK1/0 : 11
tCYC tCYC
tCYC
tCYC
tCYC
tCYC
tCYC
tCYC
Where tCYCH represents the internal clock H width and tCYCL the L width.
90
MB91F155/MB91154
(2) Reset Input Ratings (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Reset input time Symbol tRSTL Pin name RST Condition Value Min. tCP x 5 Max. Unit ns Remarks
tRSTL
RST
0.2 VCC
(3) Power On Reset (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Power supply rising time Power supply cutoff time Oscillation stabilization delay Symbol fR tOFF tOSC Pin name Condition Value Min. 2 214 tC Max. 20 Unit ms ms ns Remarks Vcc < 0.2 V before turning up the power.
VCC
tR
tOFF 0.9 x VCC
VCC
0.2 V
A rapid change in supply voltage might activate power on reset. When the supply voltage needs to be varied while operating, it is recommended to minimize fluctuations to smoothly start up the voltage.
VCC
Holding RAM data.
It is recommended to keep the rising inclination less than 50 mV/ms.
VSS
VCC
tOSC (Oscillation stabilization delay)
RST
tRSTL
When turning on the power, start the RST pin in "L" level state, allow as much time as for tRSTL after reaching the Vcc power supply level and then set the pin to the H level. 91
MB91F155/MB91154
(4) Serial I/O (CH0-4) (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Serial clock cycle time SCK SO delay time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO delay time Valid SI SCK SCK valid SI hold time Serial busy period SCS SCK and SO delay time SCS SCK input mask time SCS SCK and SO Hi-Z time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX tBUSY tCLZO tCLSL tCHOZ Pin name External clock Internal clock Condition Value Min. 8 tCPP -10 50 50 4 tCPP - 10 4 tCPP - 10 0 50 50 50 Max. 50 50 6 tCPP 50 3 tCPP Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns ns
Internal shift clock mode
tSCYC
SCK
tSLOV
SO SI
tIVSH tSHIX
External shift clock mode
tCLZO tSLSH tSHSL tBUSY tCHOZ
SCK
tSLOV
SO SI
tIVSH tSHIX
SCS
tCLSL
92
MB91F155/MB91154
(5) External Bus Measurement Conditions The following conditions apply to items that are not specifically stipulated. * AC characteristics measurement conditions VCC : 3.3 V
Input Output VIH VIL VOH VOL
VCC
VIH VIL
2.4 V 0.8 V
VOH VOL
1/2VCC 1/2VCC
0V
(The input rise/fall time is less than 10 ns.)
* Load condition
Output pin
C = 50 pF ( VCC : 3.3 V )
93
MB91F155/MB91154
(6) Normal Bus Access and Read/Write Operations (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter CS 0 - 3 delay time CS 0 - 3 delay time Address delay time Data delay time RD delay time RD delay time WR0 - 1 delay time WR0 - 1 delay time Valid address valid data input time RD valid data input time Data setup RD time RD Rdata hold time Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV tDSRH tRHDX RD D31 to D16 Pin name CLK CS0 to 3 CLK A24 to A00 CLK D31 to D16 CLK RD CLK WR0 to 1 A24 to A00 D31 to D16 Condition Value Min. 25 0 Max. 15 15 15 15 10 10 10 10 3/2x tCYC - 40 tCYC - 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns *1, *2 *1 Remarks
*1 : If the bus is extended with either automatic wait insertion or RDY input, add the (tCYC x the number of extended cycles) time to this value. *2 : This is the value at the time of (gear cycle x 1) . When the gear cycle is set to 1/2, 1/4 or 1/8, substitute "n" in the following formula with 1/2, 1/4 or 1/8 respectively. Formula : (2 - n / 2) x tCYC - 40
94
MB91F155/MB91154
tCYC BA1 VOH BA2 VOH VOH VOL
CLK
VOL
tCHCSL
tCHCSH
VOH
CS0 to CS3
VOL
tCHAV VOH VOL
A24 to A00
tCLRL
tCLRH
RD
VOH VOL
tRLDV tRHDX tAVDV VIH VIL tDSRH VIH VIL
D31 to D16
Read
tCLWL
tCLWH VOH
WR0 to WR1
VOL
tCHDV
D31 to D16
VOH VOL
Write
95
MB91F155/MB91154
(7) Ready Input Timing (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter RDY setup time CLK CLK RDY hold time Symbol tRDYS tRDYH Pin name RDY CLK RDY CLK Condition Value Min. 20 0 ns Max. Unit ns Remarks
tCYC
CLK
VOH VOL
VOH VOL
tRDYS tRDYH
tRDYS tRDYH
When RDY wait is applied
VIL
VIH
VIL
VIH
When RDY wait is not applied
VIH
VIL
VIH
VIL
96
MB91F155/MB91154
(8) Hold Timing (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter BGRNT delay time BGRNT delay time Pin floating BGRNT time BGRNT Pin valid time Symbol tCHBGL tCHBGH tXHAL tHAHV Pin name CLK BGRNT BGRNT Condition Value Min. tCYC - 10 tCYC - 10 Max. 10 10 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks
Note : More than one cycle exist after BRQ is fetched and before BGRNT changes.
tcyc
CLK
VOH
VOH
VOH
BRQ
tCHBGL
tCHBGH
BGRNT
VOH VOL
tXHAL
tHAHV
Each pin
High impedance
97
MB91F155/MB91154
(9) DMA Controller Timing (VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter DREQ input pulse width DACK delay time (typical bus) (typical DRAM) EOP delay time (typical bus) (typical DRAM) DACK delay time (Single Dram) (Hyper Dram) EOP delay time (Single Dram) (Hyper Dram) Symbol tDRWH tCLDL tCLDH tCLEL tCLEH tCHDL tCHDH tCHEL tCHEH Pin name DREQ0 to 2 CLK DACK0 to 2 CLK EOP0 to 2 CLK DACK0 to 2 CLK EOP0 to 2 Condition Value Min. 2 tCYC Max. 6 6 6 6 n / 2 x tCYC 6 n / 2 x tCYC 6 Unit ns ns ns ns ns ns ns ns ns Remarks
tcyc
VOH
CLK
VOH VOL VOL tCLDH tCLEH
tCLDL tCLEL
DACK0 - 2 EOP0 - 2 (Typical bus) (Typical DRAM)
VOH VOL
tCHDH
DACK0 - 2 EOP0 - 2 ( Single DRAM ) ( Hyper DRAM )
tCHDL tCHEL
VOH VOL
tDRWH
DREQ0 - 2
VIH
VIH
98
MB91F155/MB91154
6. A/D Converter Electrical Characteristics
(VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Resolution Conversion time Total error Linearity error Differential linearity error Zero transition error Full-scale transition error Analog input current Analog input voltage Reference voltage Conversion Supply cur- in operation rent Conversion stopped Reference voltage supply current Conversion in operation Conversion stopped Symbol VOT VFST IAIN VAIN AVRH IA AVCC IAH IR AVRH IRH AN0 to AN7 AVCC = 3.3 V AVCC = 3.3 V, AVRH = 3.3 V 2.0 5.0 3.0 10 4 A mA A LSB Pin name AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH Condition AVCC = 3.3 V, AVRH = 3.3 V Value Min. 5.1 Typ. Max. 10 4.0 3.5 2.0 Unit Bit s LSB LSB LSB Remarks
AVCC = 3.3 V, AVRH = 3.3 V
AVSS - 1.5 AVSS + 0.5 AVSS + 2.5 LSB AVRH - 5.5 AVRH - 1.5 AVRH + 0.5 LSB 0.1 3.0 10 AVRH AVCC 5.0 A V V mA
AVSS
Interchannel variation
Notes : * The smaller the |AVRH| is, the greater the error is in general. * The external circuit output impedance of analog input should be used in compliance with the following requirements : External circuit output impedance 2 (k) If the output impedance of the external circuit is too high, an analog voltage sampling duration shortage might occur. (Sampling duration = 1.4 s : @33 MHz)
99
MB91F155/MB91154
* A/D Converter Glossary * Resolution : Analog changes that are identifiable by the A/D converter. * Linearity error : The deviation of the straight line connecting the zero transition point (00 0000 0000 00 0000 0001) with the full-scale transition point (11 1111 1110 11 1111 1111) from actual conversion characteristics. * Differential linearity error : The deviation of input voltage needed to change the output code by one LSB from the theoretical value. * Total error : The difference between actual and theoretical conversion values including a zero transition/full-scale transition/linearity error.
Total error
3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB ( N - 1 ) + 0.5 LSB} 1.5 LSB
004 003 002 001 0.5 LSB AVSS AVRH VNT (Actual measurement) Actual conversion characteristics Theoretical characteristics
Analog input
1 LSB (theoretical value) = VOT (theoretical value) =
AVRH - AVSS 1024 AVSS + 0.5 LSB
[V] [V]
VFST (theoretical value) = AVRH - 1.5 LSB [V] Total error of digital output N = VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB
VNT : Voltage at which digital output changes from (N + 1) to N.
(Continued)
100
MB91F155/MB91154
(Continued)
Linearity error
3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB ( N - 1 ) + VOT} VFST (Actual measurement) Digital output N N+1 Actual conversion characteristics Theoretical characteristics
Differential linearity error
004 003 002 001 VOT (Actual measurement) AVSS Analog input AVRH VNT (Actual measurement) Actual conversion characteristics Theoretical characteristics
N-1
VNT (Actual measurement) N-2 Actual conversion characteristics Analog input
VFST (Actual measurement)
AVSS
AVRH
Linearity error of digital output N
=
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N + 1) T - VNT 1 LSB VFST - VOT 1022 -1 LSB [V]
[LSB] [LSB]
Differential linearity error = of digital output N VOT (theoretical value) =
VOT : Voltage at which digital output changes from (000) H to (001) H. VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
7. D/A Converter Electrical Characteristics
(VCC = VCC2 = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 C to +70 C) Parameter Resolution Differential linearity error Conversion time Analog output impedance * : CL = 20 pF Symbol Pin name Condition Value Min. Typ. 29 Max. 8 1 20 Unit Bit LSB s k * Remarks
101
MB91F155/MB91154
s ORDERING INFORMATION
Part number MB91F155PFV-G MB91154PFV-G-XXX Package 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) Remarks
102
MB91F155/MB91154
s PACKAGE DIMENSION
144-pin plastic LQFP (FPT-144P-M08)
22.000.30(.866.012)SQ 20.000.10(.787.004)SQ 1.70(.67)MAX (Mounting height)
73 72
108 109
0(0)MIN (STAND OFF)
17.50 (.686) REF INDEX
144 37
21.00 (.827) NOM
Details of "A" part 0.15(.006)
0.15(.006) 0.15(.006)MAX 0.40(.016)MAX "A"
LEAD No.
1
36
Details of "B" part
M
0.50(.0197)TYP
0.200.10 (.008.004)
0.08(.003)
0.150.05 (.006.002) 0 10
0.10(.004)
0.500.20(.020.008) "B"
C
2000 FUJITSU LIMITED F144019S-1C-3
Dimensions in mm (inches)
103
MB91F155/MB91154
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0101 (c) FUJITSU LIMITED Printed in Japan

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